-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 9.66 




-- ENTITY DECLARATION OF PARWAN CPU FOR ITS DATAFLOW DESCRIPTION :

LIBRARY cmos;
USE cmos.basic_utilities.ALL;
LIBRARY par_library;
USE par_library.par_utilities.ALL;
--
ENTITY par_central_processing_unit IS
  PORT (clk : IN qit;
        interrupt : IN qit;
        read_mem, write_mem : OUT qit; 
        databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve
       );
END par_central_processing_unit;
--







-- FIGURE 9.67




-- DATAFLOW ARCHITECTURE OF PARWAN CPU :

ARCHITECTURE dataflow OF par_central_processing_unit IS
  --
  COMPONENT par_data_path 
  PORT (databus : INOUT wired_byte;  adbus : OUT twelve;
        clk : IN qit;
        load_ac, zero_ac, 
        load_ir, 
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar, 
        load_sr, cm_carry_sr, 
        pc_on_mar_page_bus, ir_on_mar_page_bus, 
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
        mar_on_adbus,
        dbus_on_databus,
        arith_shift_left, arith_shift_right : IN qit;
        alu_code : IN qit_vector (2 DOWNTO 0);
        ir_lines : OUT byte; status : OUT nibble
       );
  END COMPONENT; 
  FOR data: par_data_path USE ENTITY WORK.par_data_path (structural);
  --
  COMPONENT par_control_unit
  PORT (clk : IN qit;
        load_ac, zero_ac, 
        load_ir, 
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar, 
        load_sr, cm_carry_sr, 
        pc_on_mar_page_bus, ir_on_mar_page_bus, 
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
        mar_on_adbus,
        dbus_on_databus,
        arith_shift_left, arith_shift_right : OUT qit;
        alu_code : OUT qit_vector (2 DOWNTO 0);
        ir_lines : IN byte; status : IN nibble;
        read_mem, write_mem : OUT qit; interrupt : IN qit
       );
  END COMPONENT; 
  FOR ctrl: par_control_unit USE ENTITY WORK.par_control_unit (dataflow);
  --
  SIGNAL load_ac, zero_ac, 
         load_ir, 
         increment_pc, load_page_pc, load_offset_pc, reset_pc,
         load_page_mar, load_offset_mar, 
         load_sr, cm_carry_sr, 
         pc_on_mar_page_bus, ir_on_mar_page_bus, 
         pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
         pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
         mar_on_adbus,
         dbus_on_databus,
         arith_shift_left, arith_shift_right : qit;
  SIGNAL alu_code : qit_vector (2 DOWNTO 0);
  SIGNAL ir_lines : byte; 
  SIGNAL status : nibble;
BEGIN
  data: par_data_path PORT MAP
        (databus, adbus,
         clk,
         load_ac, zero_ac, 
         load_ir, 
         increment_pc, load_page_pc, load_offset_pc, reset_pc,
         load_page_mar, load_offset_mar, 
         load_sr, cm_carry_sr, 
         pc_on_mar_page_bus, ir_on_mar_page_bus, 
         pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
         pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
         mar_on_adbus,
         dbus_on_databus, 
         arith_shift_left, arith_shift_right,
         alu_code,
         ir_lines, status
        );
  ctrl: par_control_unit PORT MAP 
        (clk,
         load_ac, zero_ac, 
         load_ir, 
         increment_pc, load_page_pc, load_offset_pc, reset_pc,
         load_page_mar, load_offset_mar, 
         load_sr, cm_carry_sr, 
         pc_on_mar_page_bus, ir_on_mar_page_bus, 
         pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
         pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
         mar_on_adbus,
         dbus_on_databus, 
         arith_shift_left, arith_shift_right,
         alu_code,
         ir_lines, status,
         read_mem, write_mem, interrupt
        );
END dataflow;
--