-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.23
-- ENTITY DECLERATION OF THE INTERFACE BETWEEN SYSTEMS
A AND B IN FIG. 8.22 :
ENTITY system_i IS
PORT (in_data : IN BIT_VECTOR (3 DOWNTO 0);
out_data : OUT BIT_VECTOR (15 DOWNTO 0);
in_ready, out_received : IN BIT;
in_received, out_ready : OUT BIT);
END system_i;
--
-- COMPLETE VHDL DESCRIPTION FOR THE D_SR_FLIPFLOP :
ARCHITECTURE waiting OF system_i IS
SIGNAL buffer_full, buffer_picked : BIT := '0';
SIGNAL word_buffer : BIT_VECTOR (15 DOWNTO 0);
BEGIN
a_talk: PROCESS
VARIABLE count : INTEGER RANGE 0 TO 4 := 0;
BEGIN
WAIT UNTIL in_ready = '1';
count := count + 1;
CASE count IS
WHEN 0 => NULL;
WHEN 1 => word_buffer (03 DOWNTO 00) <= in_data;
WHEN 2 => word_buffer (07 DOWNTO 04) <= in_data;
WHEN 3 => word_buffer (11 DOWNTO 08) <= in_data;
WHEN 4 => word_buffer (15 DOWNTO 12) <= in_data;
buffer_full <= '1';
WAIT UNTIL buffer_picked = '1';
buffer_full <= '0';
count := 0;
END CASE;
in_received <= '1';
WAIT UNTIL in_ready = '0';
in_received <= '0';
END PROCESS a_talk;
b_talk: PROCESS
BEGIN
IF buffer_full = '0' THEN WAIT UNTIL buffer_full = '1'; END IF;
out_data <= word_buffer;
buffer_picked <= '1';
WAIT UNTIL buffer_full = '0';
buffer_picked <= '0';
out_ready <= '1';
WAIT UNTIL out_received = '1';
out_ready <= '0';
END PROCESS b_talk;
END waiting;
--