-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.38
-- ENTITY DECLERATION OF SEQUENTIAL COMPARATOR :
USE WORK.basic_utilities.ALL;
--
ENTITY sequential_comparator IS
PORT (data_in : IN qit_vector (7 DOWNTO 0);
clk, clear_bar, load_bar : IN qit;
count_in : IN qit_vector (3 DOWNTO 0);
count : OUT qit_vector (3 DOWNTO 0) );
BEGIN
ASSERT NOT ( (clk='0' AND NOT clk'STABLE) AND NOT clk'DELAYED'STABLE (1 US) )
REPORT "Minimum Clock Width Violation" SEVERITY WARNING;
END sequential_comparator;
--
-- STRUCTURAL DESCRIPTION FOR SEQUENTIAL COMPARATOR :
ARCHITECTURE structural OF sequential_comparator IS
COMPONENT d_register
PORT (clk, g_bar : IN qit; d8 : IN qit_vector (7 DOWNTO 0);
q8 : OUT qit_vector (7 DOWNTO 0));
END COMPONENT;
COMPONENT comparator
PORT (a, b : IN qit_vector (3 DOWNTO 0); gt, eq, lt : IN qit;
a_gt_b, a_eq_b, a_lt_b : OUT qit);
END COMPONENT;
COMPONENT counter
PORT (clk, clr_bar, ld_bar, enp, ent : IN qit;
abcd : IN qit_vector (3 DOWNTO 0);
q_abcd : OUT qit_vector (3 DOWNTO 0); rco : OUT qit);
END COMPONENT;
SIGNAL gnd : qit := '0'; SIGNAL vdd : qit := '1';
SIGNAL old_data : qit_vector (7 DOWNTO 0);
SIGNAL compare_out : qit;
SIGNAL gt_i, eq_i, lt_i : qit;
BEGIN
reg: d_register PORT MAP (clk, gnd, data_in, old_data);
cmp_lo: comparator PORT MAP (data_in (3 DOWNTO 0), old_data (3 DOWNTO 0),
gnd, vdd, gnd, gt_i, eq_i, lt_i);
cmp_hi: comparator PORT MAP (data_in (7 DOWNTO 4), old_data (7 DOWNTO 4),
gt_i, eq_i, lt_i, OPEN, compare_out, OPEN);
cnt: counter PORT MAP (clk, clear_bar, load_bar, vdd, compare_out,
count_in, count, OPEN);
END structural;
--