-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.8
-- ENTITY DECLERATION OF SR FLIPFLOP OF FIGURE 8.6 :
ENTITY d_sr_flipflop IS
GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS);
PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT);
END d_sr_flipflop;
--
-- ALTERNATIVE VHDL DESCRIPTION FOR THE SR FLIPFLOP OF FIGURE 8.6 :
ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS
BEGIN
dff: PROCESS (rst, set, clk)
VARIABLE state : BIT := '0';
BEGIN
IF set = '1' THEN
state := '1';
ELSIF rst = '1' THEN
state := '0';
ELSIF clk = '1' AND clk'EVENT THEN
state := d;
END IF;
q <= state AFTER (sq_delay + rq_delay + cq_delay)/3;
qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay)/3;
END PROCESS dff;
END average_delay_behavioral;
--