-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.15
-- ENTITY DECLERATION OF D_SR_FLIPFLOP :
ENTITY d_sr_flipflop IS
GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS;
set_up, hold : TIME := 4 NS);
PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT);
BEGIN
ASSERT (NOT (clk = '1' AND clk'EVENT AND NOT d'STABLE(set_up) ))
REPORT "Set_up time violation" SEVERITY WARNING;
ASSERT (NOT (d'EVENT AND clk = '1' AND NOT clk'STABLE(hold) ))
REPORT "Hold time violation" SEVERITY WARNING;
END d_sr_flipflop;
--
-- COMPLETE VHDL DESCRIPTION FOR THE D_SR_FLIPFLOP :
ARCHITECTURE behavioral OF d_sr_flipflop IS
SIGNAL state : BIT := '0';
BEGIN
dff: PROCESS (rst, set, clk)
BEGIN
ASSERT (NOT (set = '1' AND rst = '1'))
REPORT "set and rst are both 1" SEVERITY WARNING;
IF set = '1' THEN
state <= '1' AFTER sq_delay;
ELSIF rst = '1' THEN
state <= '0' AFTER rq_delay;
ELSIF clk = '1' AND clk'EVENT THEN
state <= d AFTER cq_delay;
END IF;
END PROCESS dff;
q <= state;
qb <= NOT state;
END behavioral;
--