-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.7
-- ENTITY DECLERATION OF SR FLIPFLOP OF FIGURE 8.6 :
ENTITY d_sr_flipflop IS
GENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS);
PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT);
END d_sr_flipflop;
--
-- VHDL DESCRIPTION FOR THE SR FLIPFLOP OF FIGURE 8.6 :
ARCHITECTURE behavioral OF d_sr_flipflop IS
SIGNAL state : BIT := '0';
BEGIN
dff: PROCESS (rst, set, clk)
BEGIN
IF set = '1' THEN
state <= '1' AFTER sq_delay;
ELSIF rst = '1' THEN
state <= '0' AFTER rq_delay;
ELSIF clk = '1' AND clk'EVENT THEN
state <= d AFTER cq_delay;
END IF;
END PROCESS dff;
q <= state;
qb <= NOT state;
END behavioral;
--