-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.26
-- ENTITY DECLERATION OF TWO-PHASE CLOCK :
USE STD.TEXTIO.ALL;
ENTITY two_phase_clock IS END two_phase_clock;
--
-- VHDL DESCRIOPTION OF TWO-PHASE CLOCK USING DISPLAY PROCEDURE IN FIG. 8.25 :
ARCHITECTURE input_output OF two_phase_clock IS
PROCEDURE display (SIGNAL value1, value2 : BIT) IS
FILE flush : TEXT IS OUT "/dev/tty";
VARIABLE filler : STRING (1 TO 3) := " ..";
VARIABLE l : LINE;
BEGIN
WRITE (l, NOW, RIGHT, 8, NS);
IF value1'EVENT THEN
WRITE (l, value1, RIGHT, 3);
WRITE (l, filler, LEFT, 0);
ELSE
WRITE (l, filler, LEFT, 0);
WRITE (l, value2, RIGHT, 3);
END IF;
WRITELINE (flush, l);
END display;
SIGNAL c1 : BIT := '1';
SIGNAL c2 : BIT := '0';
BEGIN
phase1: c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1;
phase2: PROCESS
BEGIN
WAIT UNTIL c1 = '0';
WAIT FOR 10 NS;
c2 <= '1';
WAIT FOR 480 NS;
c2 <= '0';
END PROCESS phase2;
display (c1, c2);
END input_output;
--