-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 8.27
-- ENTITY DECLERATION OF TWO-PHASE CLOCK :
USE STD.TEXTIO.ALL;
ENTITY two_phase_clock IS END two_phase_clock;
--
-- INPUT-OUTPUT ARCHITECTURE OF OF TWO-PHASE CLOCK WITH A PROCESS STATEMENT
GENERATING A SIMULATION REPORT :
ARCHITECTURE input_output OF two_phase_clock IS
SIGNAL c1 : BIT := '1';
SIGNAL c2 : BIT := '0';
BEGIN
phase1: c1 <= NOT c1 AFTER 500 NS WHEN NOW < 4 US ELSE c1;
phase2: PROCESS
BEGIN
WAIT UNTIL c1 = '0';
WAIT FOR 10 NS;
c2 <= '1';
WAIT FOR 480 NS;
c2 <= '0';
END PROCESS phase2;
writing: PROCESS (c1, c2)
FILE flush : TEXT IS OUT "clock.out";
VARIABLE filler : STRING (1 TO 3) := " ..";
VARIABLE l : LINE;
BEGIN
WRITE (l, NOW, RIGHT, 8, NS);
IF c1'EVENT THEN
WRITE (l, c1, RIGHT, 3);
WRITE (l, filler, LEFT, 0);
ELSE
WRITE (l, filler, LEFT, 0);
WRITE (l, c2, RIGHT, 3);
END IF;
WRITELINE (flush, l);
END PROCESS writing;
END input_output;
--