-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 6.30
-- ENTITY DECLARATION OF AN INVERTER TESTER :
USE WORK.basic_utilities.ALL;
ENTITY tester IS
END tester;
--
-- INPUT-OUTPUT ARCHITECTURE OF THE TESTER
-- BY CALLING THE OVERLOADED ASSIGN_BITS :
ARCHITECTURE input_output OF tester IS
COMPONENT inv
GENERIC (c_load : capacitance := 11 ffr);
PORT (i1 : IN qit; o1 : OUT qit);
END COMPONENT;
FOR ALL : inv USE ENTITY WORK.inv_rc(double_delay);
SIGNAL a, z : qit;
BEGIN
assign_bits (a, "data.qit", 500 NS);
i1 : inv PORT MAP (a, z);
END input_output;
--