-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 6.25
-- ENTITY DECLARATION OF INVERTER :
USE WORK.basic_utilities.ALL;
ENTITY inv_q IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
PORT (i1 : IN qit; o1 : OUT qit);
END inv_q;
--
-- AVERAGE-DELAY ARCHITECTURE OF INVERTER :
ARCHITECTURE double_delay OF inv_q IS
BEGIN
o1 <= '1' AFTER tplh WHEN i1 = '0' ELSE
'0' AFTER tphl WHEN i1 = '1' OR i1 = 'Z' ELSE
'X' AFTER tplh;
END double_delay;
-- ENTITY DECLARATION OF 2-INPUT NAND GATE :
USE WORK.basic_utilities.ALL;
ENTITY nand2_q IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
PORT (i1, i2 : IN qit; o1 : OUT qit);
END nand2_q;
--
-- AVERAGE-DELAY ARCHITECTURE OF 2-INPUT NAND GATE :
ARCHITECTURE average_delay OF nand2_q IS
BEGIN
o1 <= NOT ( i1 AND i2 ) AFTER (tplh + tphl) / 2;
END average_delay;
-- ENTITY DECLARATION OF 3-INPUT NAND GATE :
USE WORK.basic_utilities.ALL;
ENTITY nand3_q IS
GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS);
PORT (i1, i2, i3 : IN qit; o1 : OUT qit);
END nand3_q;
--
-- AVERAGE-DELAY ARCHITECTURE OF 3-INPUT NAND GATE :
USE WORK.basic_utilities.ALL;
ARCHITECTURE average_delay OF nand3_q IS
BEGIN
o1 <= NOT ( i1 AND i2 AND i3) AFTER (tplh + tphl) / 2;
END average_delay;
--