-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 6.6
-- ENTITY DECLERATION OF AN 2-INPUT NAND :
USE WORK.basic_utilities.ALL;
ENTITY nand2_q IS
GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS);
PORT (i1, i2 : IN qit; o1 : OUT qit);
END nand2_q;
--
-- DOUBLE DELAY ARCHITECTURE OF THE 2-INPUT NAND IN QIT LOGICAL SYSTEM :
ARCHITECTURE double_delay OF nand2_q IS
BEGIN
o1 <= '1' AFTER tplh WHEN i1 = '0' OR i2 = '0' ELSE
'0' AFTER tphl WHEN (i1 = '1' AND i2 = '1') OR
(i1 = '1' AND i2 = 'Z') OR
(i1 = 'Z' AND i2 = '1') OR
(i1 = 'Z' AND i2 = 'Z') ELSE
'X' AFTER tplh;
END double_delay;
--