%i   "inside.sfl"
%i   "ram.sfl"

submod_class   inside {
   input     in_data<8> ;
   output    out_data<8> ;
   output    address<8> ;
   output    acc_a<8>,pc_a<8>,sp_a<8> ;
   instrin   reset ;
   instrin   start ;
   instrout  read ;
   instrout  write ;
   instr_arg reset() ;
   instr_arg start(in_data) ;
   }

submod_class ram {
   input     address<8> ;
   input     in_data<8> ;
   output    out_data<8> ;
   instrin   read ;
   instrin   write ;
   instrin   init ;
   instr_arg read(address) ;
   instr_arg write(address,in_data) ;
   instr_arg init() ;
   }

module   system {
   tmp       ram_data<8> ;
   tmp       pld_data<8> ;
   tmp       address<8> ;
   tmp       acc_a<8>,pc_a<8>,sp_a<8> ;
   instrin   reset ;
   instrin   start ;
   inside    inside0 ;
   ram       ram0 ;

   instruct reset
     /* reset condition */
     par {
       ram0.init() ;
       acc_a = inside0.reset().acc_a ;
       pc_a  = inside0.reset().pc_a ;
       sp_a  = inside0.reset().sp_a ;
       }

   instruct start
     /* start assember program */
     par {
       address   = inside0.start(ram_data).address ;
       pld_data  = inside0.start(ram_data).out_data ;
       acc_a     = inside0.start(ram_data).acc_a ;
       pc_a      = inside0.start(ram_data).pc_a ;
       sp_a      = inside0.start(ram_data).sp_a ;
       any {
         inside0.start(ram_data).read : 
           ram_data = ram0.read(address).out_data ;
         inside0.start(ram_data).write :
           ram0.write(address,pld_data) ;
         }
       }
    }