circuit_type   memory {
   input     address<8> ;
   input     in_data<8> ;
   output    out_data<8> ;
   mem       cell[256]<8> ;
   instrin   read ;
   instrin   write ;
   instrin   init  ;
   instr_arg read(address) ;
   instr_arg write(address,in_data) ;
   instr_arg init() ;

   instruct read
      out_data = cell[address] ;
   instruct write
      cell[address] := in_data ;
   instruct init
      par {
         cell[0b00000000] := 0b00000000 ; /* LOAD     #00010000 */
         cell[0b00000001] := 0b00010000 ;
         cell[0b00000010] := 0b00000001 ; /* ADD_ACC  #00010001 */
         cell[0b00000011] := 0b00010001 ;
         cell[0b00000100] := 0b10000000 ; /* PUSH               */
         cell[0b00000101] := 0b00000000 ;
         cell[0b00000110] := 0b10000001 ; /* POP                */
         cell[0b00000111] := 0b00000000 ;
         cell[0b00001000] := 0b00000010 ; /* JUMP     #00000001 */
         cell[0b00001001] := 0b00000010 ;
         cell[0b00010000] := 0b00001000 ; /* data     #00010000 */
         cell[0b00010001] := 0b00000001 ; /* data     #00010001 */
         cell[0b00010010] := 0b00000010 ; /* data     #00010010 */
         }
   }

module   ram {
   input     address<8> ;
   input     in_data<8> ;
   output    out_data<8> ;
   instrin   read ;
   instrin   write ;
   instrin   init ;
   memory    ram1 ;

   instruct read
      out_data = ram1.read(address).out_data ;
   instruct write
      par {
         ram1.write(address,in_data) ;
         out_data = 0b11111111 ; /* pulled up data */
         }
   instruct init
      ram1.init() ;
   }