%i   "inc4.sfl"

submod_class inc4 {
   input   in<4> ;
   output  out<4> ;
   instrin do ;
   instr_arg do(in) ;
   }

submod_class dec4 {
   input   in<4> ;
   output  out<4> ;
   instrin do ;
   instr_arg do(in) ;
   }

module pc4 {
   input      in<4> ;
   output     out<4> ;
   tmp        tmp<4> ;
   reg        r<4> ;
   instrin    up,load,hold,clear ;

   inc4       inc0 ;

   stage_name cnt_up {
      task    run() ;
      }

   stage_name cnt_load {
      task    run() ;
      }

   stage_name cnt_hold {
      task    run() ;
      }

   stage_name cnt_clear {
      task    run() ;
      }

   instruct up    generate cnt_up.run() ;
   instruct load  generate cnt_load.run() ;
   instruct hold  generate cnt_hold.run() ;
   instruct clear generate cnt_clear.run() ;

   stage   cnt_up {
      state_name  st1 ;
      first_state st1 ;

      state st1 par {
         tmp = inc0.do(r).out ;
         r := tmp ;
         out = r ;
         finish ;
         }
      }

   stage   cnt_load {
      state_name  st1 ;
      first_state st1 ;

      state st1 par {
         tmp = in ;
         r := tmp ;
         out = r ;
         finish ;
         }
      }

   stage   cnt_hold {
      state_name  st1 ;
      first_state st1 ;

      state st1 par {
         out = r ;
         finish ;
         }
      }

   stage   cnt_clear {
      state_name  st1 ;
      first_state st1 ;

      state st1 par {
         r := 0b0000 ;
         out = r ;
         finish ;
         }
      }
   }