README file for Volume System design example. 

Author: Preeti Ranjan Panda (ppanda@ics.uci.edu)


Description
-----------

This directory contains the Volume System design example. The model
is in the SpecCharts language (from which a VHDL model can be automatically
generated). The testbench is written in VHDL. This instantiates the VHDL
model generated from 'vol.sc'.

The contents of this directory are:

bit_functions.vhd	- VHDL package

vol.sc			- SpecCharts model for Volume System

vol.vhdl		- VHDL model generated by SpecCharts from vol.sc

vol_sim.vhdl		- VHDL testbench for generated VHDL model

README			- This file


References are provided in the report.