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Done. dater%s %s %s %s %s %sdate : %s %s, %s time : %s --------------------------------------------------------------------------- -- -- Radix-512 Divider Benchmark -- -- Test Vectors -- -- VHDL file generated by make_tv from %s -- date : %s %s, %s time : %s -- --------------------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity E is generic( simulation_delay : time := %d ns ; division_delay : time := %d ns ); end; architecture A of E is component radix512 port( x,d: in std_logic_vector (52 downto 0); q: out std_logic_vector (52 downto 0)); end component; signal x,d: std_logic_vector(52 downto 0); signal q: std_logic_vector(52 downto 0); for all : radix512 use entity work.radix512(radix512) ; begin INST1 : radix512 port map( x, d, q ); process begin wait for simulation_delay ; --------------------------------------------------------------------------- -- TEST VECTORS --------------------------------------------------------------------------- end process; end; ERROR *** x out of range ERROR *** d out of range ERROR *** x greater than d ERROR *** too many bits read x = %f, ERROR *** too many bits d = %f ERROR *** x out of range ERROR *** d out of range ERROR *** x greater than d --------------------------------------------------------------------------- -- x = %54.53f -- d = %54.53f -- q = %54.53f x <= "" ; d <= "" ; wait for division_delay; assert q = "" report "q does not match in pattern %d" severity error; 10@(#)pow.c 1.9 88/02/08 SMI?.B9?.B=95y