-------------------------------------------------------------------------- -------------------------------------------------------------------------- -- File Name : tms.v -- Author(s) : R. Vutukuru and S. Rangarajan -- Affiliation : Laboratory for Digital Design Environments -- Department of Electrical & Computer Engineering -- University of Cincinnati -- Date Created : June 1991 -- Introduction : Behavioral description of Texas Instrument's -- TMS-1000, written in a synthesizable subset -- of VHDL. -- Source : Original source from -- -- D. Siewiorek, C. Bell and A. Newell, -- ``Computer Structures: Principles and Examples'', -- McGraw-Hill, 1971. and from -- `TMS-1000 Programmer's Reference Manual,' Texas -- Instruments Inc. -- -- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati. -- Date Modified : Sept, 91. -- -- Disclaimer : This comes with absolutely no guarantees of any -- kind (just stating the obvious ...) -- -- Acknowledgement : The Distributed Synthesis Systems research at -- the Laboratory for Digital Design Environments, -- University of Cincinnati, is sponsored in part -- by the Defense Advanced Research Projects Agency -- under order number 7056 monitored by the Federal -- Bureau of Investigation under contract number -- J-FBI-89-094. -- -------------------------------------------------------------------------- -------------------------------------------------------------------------- use STD.TEXTIO.all; use work.functions.all; entity tms is -- ONLY THOSE SIGNALS WHICH APPEAR AS PINS IN THE CHIP ARE DECLARED AS PORTS port (R_0, R_1, R_2, R_3, R_4, R_5, R_6, R_7, R_8, R_9, R_10 : inout BIT; CKI_BUS : inout BIT_VECTOR(3 downto 0); PLA_OUT : inout BIT_VECTOR(7 downto 0); INIT : inout BIT); end tms; architecture tms of tms is signal stop_tms : BIT; begin p : process -- NOT FOR VSS file S_IN : TEXT is out "result"; -- NOT FOR VSS variable L : line; type ROM_ARRAY is array (0 to 1023) of BIT_VECTOR(7 downto 0); type RAM_ARRAY is array (0 to 63) of BIT_VECTOR(3 downto 0); type OUT_PLA_ARRAY is array (0 to 31) of BIT_VECTOR(7 downto 0); type INSTR_PLA_ARRAY is array (0 to 255) of BIT_VECTOR(15 downto 0); variable ROM : ROM_ARRAY; -- ROM for instruction storage variable RAM : RAM_ARRAY; -- RAM variable ram_bit : BIT_VECTOR(255 downto 0); variable first : INTEGER := 1; -- PC state variable PA : BIT_VECTOR(3 downto 0); -- Page address register variable PB : BIT_VECTOR(3 downto 0); -- Page buffer register variable PC : BIT_VECTOR(5 downto 0); -- Program counter variable one : BIT_VECTOR(5 downto 0); -- variable SR : BIT_VECTOR(5 downto 0); -- Subroutine return register variable CL : BIT; -- Call latch variable XX : BIT_VECTOR(1 downto 0); -- variable Y : BIT_VECTOR(3 downto 0); -- pointer/storage register variable S : BIT; -- Logic status variable SL : BIT; -- Conditional branch status variable A : BIT_VECTOR(3 downto 0); -- Accumulator -- variable O : BIT_VECTOR(3 downto 0); -- Output buffer -- External state variable K : BIT_VECTOR(3 downto 0) ; -- External inputs; -- Implementation declarations variable N_MUX : BIT_VECTOR(3 downto 0) ; -- Multiplexer downto adder variable P_MUX : BIT_VECTOR(3 downto 0) ; -- Multiplexer downto adder variable ADDER : BIT_VECTOR(4 downto 0) ; -- The adder/ALU alias ADDER_0 : BIT is ADDER(0) ; variable TEMP : BIT_VECTOR(3 downto 0) ; -- temporary register variable s_trace : BIT ; -- Status trace variable rom_address : BIT_VECTOR(9 downto 0) ; -- Instruction ROM address reg variable OUT_PLA : OUT_PLA_ARRAY; -- simulation of output PLA variable activate_out_pla : BIT_VECTOR(7 downto 0); -- simulation of output PLA -- simulation of output PLA variable activate_instr_pla : BIT_VECTOR(15 downto 0); alias activate_instr_pla_0 : BIT is activate_instr_pla(0); alias activate_instr_pla_1 : BIT is activate_instr_pla(1); alias activate_instr_pla_2 : BIT is activate_instr_pla(2); alias activate_instr_pla_3 : BIT is activate_instr_pla(3); alias activate_instr_pla_4 : BIT is activate_instr_pla(4); alias activate_instr_pla_5 : BIT is activate_instr_pla(5); alias activate_instr_pla_6 : BIT is activate_instr_pla(6); alias activate_instr_pla_7 : BIT is activate_instr_pla(7); alias activate_instr_pla_8 : BIT is activate_instr_pla(8); alias activate_instr_pla_9 : BIT is activate_instr_pla(9); alias activate_instr_pla_10 : BIT is activate_instr_pla(10); alias activate_instr_pla_11 : BIT is activate_instr_pla(11); alias activate_instr_pla_12 : BIT is activate_instr_pla(12); alias activate_instr_pla_13 : BIT is activate_instr_pla(13); alias activate_instr_pla_14 : BIT is activate_instr_pla(14); alias activate_instr_pla_15 : BIT is activate_instr_pla(15); variable dummy : BIT_VECTOR(9 downto 0); -- variable INSTR_PLA : INSTR_PLA_ARRAY; -- simulation of instruction PLA variable b_rev : BIT_VECTOR(1 downto 0); -- Reverse bit b field; variable c_rev : BIT_VECTOR(3 downto 0); -- Reverse bit c field; -- Instruction format variable I_BUS : BIT_VECTOR(7 downto 0) ; -- Doubles as instruction register alias ADD3 : BIT_VECTOR(3 downto 0) is ADDER(3 downto 0); alias ADD_0 : BIT is ADDER(0); alias op_I : BIT_VECTOR(1 downto 0) is I_BUS(7 downto 6); alias w : BIT_VECTOR(5 downto 0) is I_BUS(5 downto 0); alias op_II : BIT_VECTOR(3 downto 0) is I_BUS(7 downto 4); alias c : BIT_VECTOR(3 downto 0) is I_BUS(3 downto 0); alias op_III : BIT_VECTOR(5 downto 0) is I_BUS(7 downto 2); alias b : BIT_VECTOR(1 downto 0) is I_BUS(1 downto 0); alias op_IV : BIT_VECTOR(7 downto 0) is I_BUS(7 downto 0); alias op_V : BIT_VECTOR(4 downto 0) is I_BUS(7 downto 3); alias f : BIT_VECTOR(2 downto 0) is I_BUS(2 downto 0); -- variable test_loop : INTEGER; -- variable I : INTEGER; procedure init_out_pla(variable OUT_PLA : out OUT_PLA_ARRAY ) is begin OUT_PLA(0) := "00000000" ; OUT_PLA(1) := "00000001" ; OUT_PLA(2) := "00000010" ; OUT_PLA(3) := "00000011" ; OUT_PLA(4) := "00000100" ; OUT_PLA(5) := "00000101" ; OUT_PLA(6) := "00000110" ; OUT_PLA(7) := "00000111" ; OUT_PLA(8) := "00001000" ; OUT_PLA(9) := "00001001" ; OUT_PLA(10) := "00001010" ; OUT_PLA(11) := "00001011" ; OUT_PLA(12) := "00001100" ; OUT_PLA(13) := "00001101" ; OUT_PLA(14) := "00001110" ; OUT_PLA(15) := "00001111" ; OUT_PLA(16) := "01111110" ; OUT_PLA(17) := "00110000" ; OUT_PLA(18) := "01101101" ; OUT_PLA(19) := "01111001" ; OUT_PLA(20) := "00110011" ; OUT_PLA(21) := "01011011" ; OUT_PLA(22) := "01011111" ; OUT_PLA(23) := "01110000" ; OUT_PLA(24) := "01111111" ; OUT_PLA(25) := "01111011" ; OUT_PLA(26) := "01110111" ; OUT_PLA(27) := "00011111" ; OUT_PLA(28) := "01001110" ; OUT_PLA(29) := "00111101" ; OUT_PLA(30) := "01001111" ; OUT_PLA(31) := "01000111" ; end init_out_pla; procedure init_loop(variable INSTR_PLA : out INSTR_PLA_ARRAY ) is variable tempy : BIT_VECTOR(7 downto 0 ); variable tempy1 : BIT_VECTOR(7 downto 0 ); begin tempy := "01000000" ; INSTR_PLA(bits_to_int(tempy)) := "0001111111001010" ; tempy := "01010000" ; INSTR_PLA(bits_to_int(tempy)) := "0010111110101000" ; tempy := "01100000" ; INSTR_PLA(bits_to_int(tempy)) := "0110111111000010" ; tempy := "01110000" ; INSTR_PLA(bits_to_int(tempy)) := "0001110111010000" ; end init_loop; procedure init_instr_pla(variable INSTR_PLA : out INSTR_PLA_ARRAY ) is begin INSTR_PLA(1) := "0001101111011100" ; INSTR_PLA(2) := "0010101111101001" ; INSTR_PLA(3) := "1011111111001000" ; INSTR_PLA(4) := "1011111111001100" ; INSTR_PLA(5) := "0001101111011100" ; INSTR_PLA(6) := "0001101111011100" ; INSTR_PLA(7) := "0001101111010100" ; INSTR_PLA(8) := "0001111111001100" ; INSTR_PLA(9) := "0001101111011100" ; INSTR_PLA(10) := "0011101111000100" ; INSTR_PLA(32) := "1010111111000010" ; INSTR_PLA(33) := "0011011111001100" ; INSTR_PLA(34) := "0001101111011010" ; INSTR_PLA(35) := "0010111111001100" ; INSTR_PLA(36) := "0011101110111010" ; INSTR_PLA(37) := "0011001111011100" ; INSTR_PLA(38) := "0011011111101000" ; INSTR_PLA(39) := "0011010111010100" ; INSTR_PLA(40) := "0011011111010100" ; INSTR_PLA(41) := "0011010111010000" ; INSTR_PLA(42) := "0011011101011100" ; INSTR_PLA(43) := "0010111111010010" ; INSTR_PLA(44) := "0010111101011010" ; INSTR_PLA(45) := "0011110111010100" ; INSTR_PLA(46) := "1011011111001100" ; INSTR_PLA(47) := "0011111111001100" ; INSTR_PLA(56) := "0001011110101000" ; INSTR_PLA(57) := "0001011110101000" ; INSTR_PLA(58) := "0001011110101000" ; INSTR_PLA(59) := "0001011110101000" ; TEMP := "0000" ; init_loop(INSTR_PLA); end init_instr_pla; procedure noop is begin end; procedure BR is begin -- NOT FOR VSS write(L,string'("**** BR ****")); -- NOT FOR VSS writeline(S_IN,L); case S is when '0' => S := '1'; when '1' => if ( CL = '0') then PA := PB; PC := w; end if; when others => end case; -- NOT FOR VSS write(L,string'("**** PC VALUE ****")); -- NOT FOR VSS writeline(S_IN,L); -- NOT FOR VSS write(L,PC); -- NOT FOR VSS writeline(S_IN,L); end BR; procedure C_ALL is variable opcode : INTEGER; begin -- NOT FOR VSS write(L,string'("**** CALL ****")); -- NOT FOR VSS writeline(S_IN,L); if ( S = '1' and CL = '0') then opcode := 1; end if; if ( S = '1' and CL = '1') then opcode := 2; end if; case opcode is when 1 => SR := PC; TEMP := PA; PA := PB; PB := TEMP; PC := w; CL := '1'; when 2 => PC := w; PB := PA; when others => S := '1'; end case; -- NOT FOR VSS write(L,string'("**** PC VALUE ****")); -- NOT FOR VSS writeline(S_IN,L); -- NOT FOR VSS write(L,PC); -- NOT FOR VSS writeline(S_IN,L); end C_ALL; procedure RETN is begin -- NOT FOR VSS write(L,string'("**** RETN ****")); -- NOT FOR VSS writeline(S_IN,L); if ( CL = '1') then PC := SR; end if; PA := PB; CL := '0'; -- NOT FOR VSS write(L,string'("**** PC VALUE ****")); -- NOT FOR VSS writeline(S_IN,L); -- NOT FOR VSS write(L,PC); -- NOT FOR VSS writeline(S_IN,L); end RETN ; procedure LDP is begin -- NOT FOR VSS write(L,string'("**** LDP ****")); -- NOT FOR VSS writeline(S_IN,L); PB := c_rev; end LDP; procedure LDX is begin -- NOT FOR VSS write(L,string'("**** LDX ****")); -- NOT FOR VSS writeline(S_IN,L); XX := b_rev; -- NOT FOR VSS write(L,XX); -- NOT FOR VSS writeline(S_IN,L); end LDX; procedure COMX is begin -- NOT FOR VSS write(L,string'("**** COMX ****")); -- NOT FOR VSS writeline(S_IN,L); XX := not XX; -- NOT FOR VSS write(L,XX); -- NOT FOR VSS writeline(S_IN,L); end COMX; PROCEDURE TDO is variable dummy : BIT_VECTOR(4 downto 0); alias dummy_4 : BIT is dummy(4); alias dummy3 : BIT_VECTOR(3 downto 0) is dummy(3 downto 0); begin -- NOT FOR VSS write(L,string'("**** TDO ****")); -- NOT FOR VSS writeline(S_IN,L); dummy_4 := SL; dummy3 := A; activate_out_pla := OUT_PLA(bits_to_int(dummy)); PLA_OUT <= activate_out_pla; wait for 1 ns; end TDO; procedure CLO is begin -- NOT FOR VSS write(L,string'("**** CLO ****")); -- NOT FOR VSS writeline(S_IN,L); activate_out_pla := OUT_PLA(0); PLA_OUT <= activate_out_pla; wait for 1 ns; -- NOT FOR VSS write(L,activate_out_pla) ; -- NOT FOR VSS writeline(S_IN,L) ; end CLO; procedure SETR is variable count : Integer; begin -- NOT FOR VSS write(L,string'("**** SETR ****")); -- NOT FOR VSS writeline(S_IN,L); if not (bits_to_int(Y) > 2) then count := bits_to_int(Y); case count is when 0 => R_0 <= '1'; when 1 => R_1 <= '1'; when others => noop; -- never occurrs end case; wait for 1 ns; end if; -- NOT FOR VSS write(L,R(bits_to_int(Y))); -- NOT FOR VSS writeline(S_IN,L); end SETR; procedure RSTR is variable count : Integer; begin -- NOT FOR VSS write(L,string'("**** RSTR ****")); -- NOT FOR VSS writeline(S_IN,L); if not (bits_to_int(Y) > 2) then count := bits_to_int(Y); case count is when 0 => R_0 <= '0'; when 1 => R_1 <= '0'; when others => noop; -- never occurrs end case; wait for 1 ns; end if; -- NOT FOR VSS write(L,R(bits_to_int(Y))); -- NOT FOR VSS writeline(S_IN,L); end RSTR; procedure SBIT is variable dummy : BIT_VECTOR(7 downto 0); alias dummy7to6 : BIT_VECTOR(1 downto 0) is dummy(7 downto 6); alias dummy5to2 : BIT_VECTOR(3 downto 0) is dummy(5 downto 2); alias dummy_1 : BIT is dummy(1); alias dummy_0 : BIT is dummy(0); alias XX1 : BIT_VECTOR(1 downto 0) is XX(1 downto 0); alias Y3 : BIT_VECTOR(3 downto 0) is Y(3 downto 0); begin -- NOT FOR VSS write(L,string'("**** SBIT ****")); -- NOT FOR VSS writeline(S_IN,L); dummy7to6 := XX1; dummy5to2 := Y3; dummy_1 := b_rev(1); dummy_0 := b_rev(0); ram_bit(bits_to_int(dummy)) := '1'; -- NOT FOR VSS write(L,ram_bit(bits_to_int(dummy))); -- NOT FOR VSS writeline(S_IN,L); end SBIT; procedure RBIT is variable dummy : BIT_VECTOR(7 downto 0); alias dummy7to6 : BIT_VECTOR(1 downto 0) is dummy(7 downto 6); alias dummy5to2 : BIT_VECTOR(3 downto 0) is dummy(5 downto 2); alias dummy_1 : BIT is dummy(1); alias dummy_0 : BIT is dummy(0); alias XX1 : BIT_VECTOR(1 downto 0) is XX(1 downto 0); alias Y3 : BIT_VECTOR(3 downto 0) is Y(3 downto 0); begin -- NOT FOR VSS write(L,string'("**** RBIT ****")); -- NOT FOR VSS writeline(S_IN,L); dummy7to6 := XX1; dummy5to2 := Y3; dummy_1 := b_rev(1); dummy_0 := b_rev(0); ram_bit(bits_to_int(dummy)) := '1'; -- NOT FOR VSS write(L,ram_bit(bits_to_int(dummy))); -- NOT FOR VSS writeline(S_IN,L); end RBIT; procedure microexec is variable dummy : BIT_VECTOR(5 downto 0); alias dummy_5 : BIT is dummy(5); alias dummy_4 : BIT is dummy(4); alias dummy_3 : BIT is dummy(3); alias dummy_2 : BIT is dummy(2); alias dummy_1 : BIT is dummy(1); alias dummy_0 : BIT is dummy(0); alias XX_1 : BIT is XX(1); alias XX_0 : BIT is XX(0); alias Y_3 : BIT is Y(3); alias Y_2 : BIT is Y(2); alias Y_1 : BIT is Y(1); alias Y_0 : BIT is Y(0); variable dummy5 : BIT_VECTOR(4 downto 0); -- variable I : INTEGER; begin activate_instr_pla := INSTR_PLA(bits_to_int(I_BUS)); P_MUX := "0000"; N_MUX := "0000"; dummy_5 := XX_1; dummy_4 := XX_0; dummy_3 := Y_3; dummy_2 := Y_2; dummy_1 := Y_1; dummy_0 := Y_0; if ( activate_instr_pla_0 = '1') then RAM(bits_to_int(dummy)) := A; -- NOT FOR VSS write(L,string'("**** STO ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( activate_instr_pla_1 = '1') then RAM(bits_to_int(dummy)) := CKI_BUS; -- NOT FOR VSS write(L,string'("**** CKM ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_2 = '1') then RAM(bits_to_int(dummy)) := CKI_BUS; P_MUX := CKI_BUS; -- NOT FOR VSS write(L,string'("**** CKP ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_3 = '1') then RAM(bits_to_int(dummy)) := CKI_BUS; P_MUX := Y; -- NOT FOR VSS write(L,string'("**** YTP ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_4 = '1') then P_MUX := RAM(bits_to_int(dummy)); -- NOT FOR VSS write(L,string'("**** MTP ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_5 = '1') then N_MUX := A; -- NOT FOR VSS write(L,string'("**** ATN ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_6 = '1') then N_MUX := not A; -- NOT FOR VSS write(L,string'("**** NATN ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_7 = '1') then N_MUX := RAM(bits_to_int(dummy)); -- NOT FOR VSS write(L,string'("**** MTN ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_8 = '1') then N_MUX := "1111"; -- NOT FOR VSS write(L,string'("**** TN15 ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_9 = '1') then N_MUX := CKI_BUS; -- NOT FOR VSS write(L,string'("**** CKN ****")); -- NOT FOR VSS writeline(S_IN,L); end if; ADDER := P_MUX + N_MUX; if ( activate_instr_pla_10 = '1') then if (P_MUX = N_MUX) then S := '0'; else S := '1'; end if; s_trace := '1'; -- NOT FOR VSS write(L,string'("**** NE ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( activate_instr_pla_11 = '1') then S := ADDER_0; s_trace := '1'; -- NOT FOR VSS write(L,string'("**** CB **** ")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( not activate_instr_pla_12 = '1') then ADDER := P_MUX + N_MUX; dummy5 := "00001"; ADDER := ADDER + dummy5; -- NOT FOR VSS write(L,string'("**** CIN ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( activate_instr_pla_13 = '1') then A := ADD3; -- NOT FOR VSS write(L,string'("**** AUTA ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( activate_instr_pla_14 = '1') then Y := ADD3; -- NOT FOR VSS write(L,string'("**** AUTY ****")); -- NOT FOR VSS writeline(S_IN,L); end if; if ( activate_instr_pla_15 = '1') then SL := S; -- NOT FOR VSS write(L,string'("**** STSL ****")); -- NOT FOR VSS writeline(S_IN,L); end if; end microexec; procedure start is variable opcode : INTEGER; variable temp,temp1 : BIT_VECTOR(7 downto 0) ; alias rom_address9to6 : BIT_VECTOR(3 downto 0) is rom_address(9 downto 6); alias rom_address5to0 : BIT_VECTOR(5 downto 0) is rom_address(5 downto 0); begin if first = 1 then init_instr_pla(INSTR_PLA); init_out_pla(OUT_PLA); PC := "000000"; R_0 <= '0'; R_1 <= '0'; R_2 <= '0'; R_3 <= '0'; R_4 <= '0'; R_5 <= '0'; R_6 <= '0'; R_7 <= '0'; R_8 <= '0'; R_9 <= '0'; R_10 <= '0'; wait for 1 ns; CL := '0'; PA := "1111"; PB := "1111"; S := '1'; first := 0; wait for 5ns; end if ; s_trace := '0'; rom_address5to0 := PC; rom_address9to6 := PA; I_BUS := ROM(bits_to_int(rom_address)); b_rev := b; c_rev := c; PC := PC + one; temp := "00000111" ; if (not (bits_to_int(I_BUS) < 0) and (not (bits_to_int(I_BUS) > bits_to_int(temp)))) then opcode := 1; end if; temp := "00001000"; temp1:= "00001111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 2; end if; temp := "00100000"; temp1:= "00101111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 3; end if; temp := "00110000"; temp1:= "00111000"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 4; end if; temp := "01000000"; temp1:= "01111111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 5; end if; case opcode is when 1 => CKI_BUS <= c_rev; wait for 1 ns; when 2 => CKI_BUS <= K; wait for 1 ns; when 3 => CKI_BUS <= "0000"; wait for 1 ns; when 4 => case (bits_to_int(b_rev)) is when 0 => CKI_BUS <= "1110"; wait for 1 ns; when 1 => CKI_BUS <= "1101"; wait for 1 ns; when 2 => CKI_BUS <= "1011"; wait for 1 ns; when 3 => CKI_BUS <= "0111"; wait for 1 ns; when others => noop; end case; when 5 => CKI_BUS <= c_rev; wait for 1 ns; when others => noop; end case; opcode := 0; temp := "00000000"; if (bits_to_int(I_BUS) = bits_to_int(temp)) then opcode := 1; end if; temp := "00001010"; if (bits_to_int(I_BUS) = bits_to_int(temp)) then opcode := 2; end if; temp := "00001011"; if (bits_to_int(I_BUS) = bits_to_int(temp)) then opcode := 3; end if; temp := "00001100"; if (bits_to_int(I_BUS) = bits_to_int(temp)) then opcode := 4; end if; temp := "00001101"; if (bits_to_int(I_BUS) = bits_to_int(temp)) then opcode := 5; end if; temp := "00001111"; if (bits_to_int(I_BUS) = bits_to_int(temp)) then opcode := 6; end if; temp := "00010000"; temp1 := "00011111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 7; end if; temp := "00110000"; temp1 := "00110011"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 8; end if; temp := "00110100"; temp1 := "00110111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 9; end if; temp := "00111011"; temp1 := "00111111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 10; end if; temp:="10000000"; temp1:="10101111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 11; end if; temp:="10110000"; temp1:="11111111"; if (not (bits_to_int(I_BUS) < bits_to_int(temp)) and not (bits_to_int(I_BUS) > bits_to_int(temp1))) then opcode := 12; end if; case opcode is when 1 => COMX; when 2 => TDO; when 3 => CLO; when 4 => RSTR; when 5 => SETR; when 6 => RETN; when 7 => LDP; when 8 => SBIT; when 9 => RBIT; when 10 => LDX; when 11 => BR; when 12 => C_ALL; when others => microexec; end case; end start; begin -- PROCESS starts one := "000001"; Y := "0010"; --LDX dummy := "1111000000"; ROM(bits_to_int(dummy)) := "00111111"; --COMX dummy := "1111000001"; ROM(bits_to_int(dummy)) := "00000000"; --LDP dummy := "1111000010"; ROM(bits_to_int(dummy)) := "00011111"; --LDX dummy := "1111000011"; ROM(bits_to_int(dummy)) := "00111111"; --COMX dummy := "1111000100"; ROM(bits_to_int(dummy)) := "00000000"; --CALL dummy := "1111000101"; ROM(bits_to_int(dummy)) := "11100000"; --LDX dummy := "1111000110"; ROM(bits_to_int(dummy)) := "00111111"; --SETR dummy := "1111000111"; ROM(bits_to_int(dummy)) := "00001101"; --RSTR dummy := "1111001000"; ROM(bits_to_int(dummy)) := "00001100"; --SBIT dummy := "1111001001"; ROM(bits_to_int(dummy)) := "00110000"; --RBIT dummy := "1111001010"; ROM(bits_to_int(dummy)) := "00110111"; -- TDO dummy := "1111001011"; ROM(bits_to_int(dummy)) := "00001010"; -- CLO dummy:= "1111001100" ; ROM(bits_to_int(dummy)) := "00001011"; -- MICROEXEC dummy:= "1111001101" ; ROM(bits_to_int(dummy)) := "00000001"; -- MICROEXEC dummy:= "1111001110" ; ROM(bits_to_int(dummy)) := "00000010"; -- MICROEXEC dummy:= "1111001111" ; ROM(bits_to_int(dummy)) := "00000011"; -- MICROEXEC dummy:= "1111010000" ; ROM(bits_to_int(dummy)) := "00000100"; -- MICROEXEC dummy:= "1111010001" ; ROM(bits_to_int(dummy)) := "00000101"; -- MICROEXEC dummy:= "1111010010" ; ROM(bits_to_int(dummy)) := "00000110"; -- MICROEXEC dummy:= "1111010011" ; ROM(bits_to_int(dummy)) := "00000111"; -- MICROEXEC dummy:= "1111010100" ; ROM(bits_to_int(dummy)) := "00001000"; -- MICROEXEC dummy:= "1111010101" ; ROM(bits_to_int(dummy)) := "00001001"; -- BRanvh to the first instruction dummy:= "1111010110" ; ROM(bits_to_int(dummy)) := "10000000"; -- Subroutine starts --LDX dummy := "1111100000"; ROM(bits_to_int(dummy)) := "00111111"; --COMX dummy := "1111100001"; ROM(bits_to_int(dummy)) := "00000000"; --RETN dummy := "1111100010"; ROM(bits_to_int(dummy)) := "00001111"; start; end process ; end tms;