--------------------------------------------------------------------------
--------------------------------------------------------------------------
--	File Name 	: move_mc.v
--	Author(s)	: Jay(anta) Roy
--	Affiliation	: Laboratory for Digital Design Environments
--			  Department of Electrical & Computer Engineering
--			  University of Cincinnati
--	Date Created	: October 1991
--	Introduction	: Behavioral description of the Move Machine,
--			  written in a synthesizable subset of VHDL.
--	Source		: Original description in ISPS written by --
--			  P. J. Drongowski, ``An Organization-Level Story 
--			  Board for Agent - A VLSI Designer's Assistant'', 
--			  Internal Report, DSRG, CES Dept,
--			  Case Western Reserve University, Jan 1987.
--
--	Disclaimer	: This comes with absolutely no guarantees of any
--			  kind (just stating the obvious ...)
--
--      Acknowledgement : The Distributed Synthesis Systems research at 
--                        the Laboratory for Digital Design Environments,
--                        University of Cincinnati, is sponsored in part 
--                        by the Defense Advanced Research Projects Agency 
--                        under order number 7056 monitored by the Federal 
--                        Bureau of Investigation under contract number 
--                        J-FBI-89-094.
--
--------------------------------------------------------------------------
--------------------------------------------------------------------------
Library Mcc;
Use Mcc.C_Interface.All;

entity move_mc is
end move_mc;

use Work.functions.all;

architecture behavior of move_mc is
  type MEM is array (0 to 15) of BIT_VECTOR(7 downto 0);
  signal Memory : MEM := ( "10001111", "00010000", "11111111", "01000101",
                           "11000000", "00000000", "00000000", "00000000",
                           "00000000", "00000000", "00000000", "00000000",
                           "00000000", "00000000", "00000000", "10000001");

  signal IP     : INTEGER :=0;
  signal IR     : BIT_VECTOR(7 downto 0);
  signal RGST	: BIT_VECTOR(7 downto 0) := "00000000";
  signal ea     : INTEGER;
  signal fetch, decode, execute, halt : BIT;

  alias IR_ea   : BIT_VECTOR(3 downto 0) is IR(3 downto 0);

  procedure modify_ip(signal EffAdd : INTEGER;signal InstPtr : inout INTEGER) is
  begin
    if (EffAdd = InstPtr + 1) then -- must have been an immediate mode
	InstPtr <= InstPtr + 2;
    else
	InstPtr <= InstPtr + 1;
    end if;
  end modify_ip;

begin
  FET : process      -- fetch
  begin
    IR <= Memory(IP);
    decode <= '1' after 1 ns;              -- signal decode to start
    wait until not fetch'QUIET;
  end process;

  DEC : process         -- decode
    variable word : BIT_VECTOR(7 downto 0);
    alias ea_word : BIT_VECTOR(3 downto 0) is word(3 downto 0);
    alias addr_code : BIT_VECTOR(1 downto 0) is IR(5 downto 4);
  begin
    wait until not decode'QUIET;
    case addr_code is
      when "00" =>                -- absolute
	ea <= bits_to_int(IR_ea);
      when "01" =>                -- immediate
	ea <= IP + 1;
      when "10" =>                -- indirect
	word := Memory(bits_to_int(IR_ea));
	ea <= bits_to_int(ea_word);
      when "11" =>                -- IP relative
	ea <= IP + bits_to_int(IR_ea);
    end case;
    execute <= '1' after 1 ns;             -- start execute
  end process;

  EXE : process         -- execute
    alias op_code : BIT_VECTOR(1 downto 0) is IR(7 downto 6);
  begin
    wait until not execute'QUIET;
    modify_ip(ea,IP);
    if op_code = "00" then      -- load register
	RGST <= Memory(ea);
	fetch <= '1' after 1 ns;
    elsif op_code = "01" then   -- store register
	Memory(ea) <= RGST;
	fetch <= '1' after 1 ns;
    elsif op_code = "10" then   -- jump
	IP <= bits_to_int(IR_ea);
	fetch <= '1' after 1 ns;
    elsif op_code = "11" then   -- halt
	halt <= '1';
    end if;
  end process;
end behavior;