--------------------------------------------------------------------------
--------------------------------------------------------------------------
--      File Name       : encoder.v (see also, decoder.v, noise.v)
--      Author(s)       : Paul R. Joslin
--      Affiliation     : Laboratory for Digital Design Environments
--			  Department of Electrical & Computer Engineering
--			  University of Cincinnati
--      Date Created    : June 1991
--      Introduction    : Behavioral description of encoder written in
--                        a synthesiszable subset of VHDL. It is part
--                        of the `Error Correction System'.
--      Source          : Original HardwareC version obained from
--                        the HLSW repository.
--
--      Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
--      Date Modified   : Sept, 91.
--
--      Disclaimer      : This comes with absolutely no guarantees of any
--                        kind (just stating the obvious ...)
--
--      Acknowledgement : The Distributed Synthesis Systems research at
--                        the Laboratory for Digital Design Environments,
--                        University of Cincinnati, is sponsored in part
--                        by the Defense Advanced Research Projects Agency
--                        under order number 7056 monitored by the Federal
--                        Bureau of Investigation under contract number
--                        J-FBI-89-094.
--
--------------------------------------------------------------------------
--------------------------------------------------------------------------

-- necessary types in one package
package types is
    type Byte is array(0 to 7) of BIT;
    type Word is array(0 to 15) of BIT;
    type Three_bit is array(0 to 2) of BIT;
    type Two_bit is array(0 to 1) of BIT;
end types;

-- encoder
-- Transforms parallel data_in to serial stream, 
-- padded with parity checking
-- One change was made to the HardwareC description:
-- the system seems to use an implicit clock to strobe the 
-- serial data stream.  An explicit signal is used in encoder/decoder
-- instead.
use Work.types.all;
entity encoder is
    port(data_in : in Byte; -- parallel data in
         new_data: in BIT;                       -- begin encoding
         encoder_out: out BIT;                   -- serial data out
         data_ready: out BIT;                    -- begin serial data out
         strobe: out BIT);                       -- next serial bit out
end encoder;

architecture encoder_behavior of encoder is

-- Note: I could never get vss to recognize a call to this procedure.
-- I tried putting it in both the arch_declarative region and the in
-- process declaration region.  I finally had to substitute this text in.
    procedure WIDE_XOR(a, b, c, d :  in BIT; result : out Bit) is
        variable X4_i : Bit := '0';
    begin
	X4_i := X4_i xor a;
	X4_i := X4_i xor b;
	X4_i := X4_i xor c;
	X4_i := X4_i xor d;
	result := X4_i;
    end WIDE_XOR;

begin
proc1:	process
    variable i : integer;
    variable output_data : Word;
    variable zero : BIT;

begin

    zero := '0';
    wait on new_data until new_data  = '1';  -- Wait for incoming data
    data_ready <= '0';  -- signal start of process

    output_data(8) := '0';
    output_data(15) := '0';
    i := 8;
    while (i > 0) loop
      i := i -1;
      output_data(i) := data_in(i);
    end loop;
      

-- the i = '0' case
	WIDE_XOR(output_data(0),
		 output_data(1),
		 output_data(2),
		 '0',
		 output_data(9));
        WIDE_XOR(output_data(0),
                 output_data(3),
                 output_data(6),
                 '0',
                 output_data(12));
        WIDE_XOR(output_data(0),
                 output_data(1),
                 output_data(2),
                 output_data(15),
                 output_data(15));
-- the i = '1' case
        WIDE_XOR(output_data(3),
                 output_data(4),
                 output_data(5),
                 '0',
                 output_data(10));
        WIDE_XOR(output_data(1),
                 output_data(4),
                 output_data(7),
                 '0',
                 output_data(13));
        WIDE_XOR(output_data(3),
                 output_data(4),
                 output_data(5),
                 output_data(15),
                 output_data(15));
-- the i = '2' case
        WIDE_XOR(output_data(6),
                 output_data(7),
                 output_data(8),
                 '0',
                 output_data(11));
        WIDE_XOR(output_data(2),
                 output_data(5),
                 output_data(8),
                 '0',
                 output_data(14));
        WIDE_XOR(output_data(6),
                 output_data(7),
                 output_data(8),
                 output_data(15),
                 output_data(15));
    -- write output stream, the first bit is 
    -- indicated by a pulse in data_ready
    data_ready <= '1';
    wait for 1 ns;
    data_ready <= '0';
    wait for 1 ns;
    i := 0;
    while i < 16 loop
        strobe <= '0';
        wait for 1 ns;
        encoder_out <= output_data(i);
        strobe <= '1';
    end loop;
    strobe <= '0';

end process;

end encoder_behavior;