November 1, 1991
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If you are copying these benchmarks and would like to be on
our mailing list for corrections and updates, please send a
mail to "ddel@thor.ece.uc.edu".

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The best way to copy this stuff is to get the compressed tar files in each
of the following directories:

Vhdl :  contains the benchmarks.
Docs :  contains a document describing the benchmarks; should be read.
Parser: a parser for the our VHDL subset.

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Welcome to the University of Cincinnati VHDL Synthesis Benchmark Suite.
All the benchmarks are written using a behavioral subset of VHDL
and, we believe, are simulatable.  The benchmarks are described 
in the following document:
  
  Ranga Vemuri, P. Mamtora, and J. Roy, "Benchmarks for
  High-Level Synthesis", TM-ECE-DDE-91-11, Lab. for Digital
  Design Environments, Electrical and Computer Engg, 
  University of Cincinnati, June 1991.

This document is available in the directory 'Docs'.  If you
are going to use the benchmarks, you will find this document 
useful.

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(I) BENCHMARK LIST :

The benchmarks are classified into three categories :

 (A) Control Dominated Descriptions
 (B) Arithmetic Dominated Descriptions
 (C) Miscellaneous


Benchmarks in each of these categories are --

 (A) Control Dominated Descriptions :

    (1) Mark1 (40 lines of VHDL code).
    (2) Move Machine (80 lines).
    (3) Frisc Processor (300 lines).
    (4) FM-8501 Processor (320 lines).
    (5) Viper Microprocessor (480 lines).
    (6) Intel's I8251 (770 lines).
    (7) Texas Instrument's TMS-1000 (870 lines).
    (8) Motorola 68000 (incomplete) (1270 lines)

We have two more processor descriptions (MCS 6502 and Intel 8080) 
not included in this suite at this time.  We are still testing
them and may include them in the suite later.

 (B) Datapath Dominated Descriptions :

    (9) Tseng's Example (100 lines).
   (10) Differential Equation Solver (70 lines).
   (11) Elliptic Wave Filter (60 lines).
   (12) Error Correction System - It is composed of three parts
	(12a) Noise Generator (15 lines).
	(12b) Encoder (120 lines).
        (12c) Decoder (170 lines).

 (C) Miscellaneous Descriptions :

   (13) Blackjack Machine (90 lines).
   (14) Elevator Controller (60 lines).

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(II) SIMULATING THE BENCHMARKS :

Most of the above descriptions use certain functions and procedures
that are pre-defined and/or understood in the synthesis paradigm. Thus,
for proper simulation of these description, some of the pre-defined 
functions and procedures used in the above descriptions have been 
incorporated as a separate VHDL package in the file "Vhdl/pred_fns.v". For
proper simulation of any of the above descriptions, one needs to
compile this package first (if using Intermetrics VHDL simulator, 
one needs to analyze and module generate the package).

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(III) SYNTHESIZABILITY OF THE BENCHMARKS :

All of the above descriptions have been processed by the front-end of
our synthesis system DSS (Distributed Synthesis System). 
DSS has been used to produce fabricatable
designs for the Viper, Move Machine, Traffic Light Controller and
other smaller examples. In addition to the Benchmarks, we are
providing the source code for the DSS parser. All files of this
parser are in the directory "Parser". The parser is written in GNU C++,
and can be built by compiling the file "vhdl_par.cc" using the GNU
C++ compiler. Run the shell script file "build" to build the parser or,
use the following command to build the parser (g++ is assummed to be
the GNU C++ compiler) :

  $ g++ -o vhdl_syn_par vhdl_par.cc -lm -DPARENT


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(IV) DOCUMENTS :

Following is a partial list of reports on the Distributed High-Level 
Synthesis Systems research at the Laboratory for Digital Design  
Environments, University of Cincinnati. Hardcopies or softcopies 
of any of these documents can be obtained by sending a request to
Email: ddel@thor.ece.uc.edu).

 (1) Ranga Vemuri, "Distributed Synthesis Systems Research: Goals,
     Methods and Status", TM-ECE-DDE-91-15 (revised), pp. 12,
     Laboratory for Digital Design Environments, Dept of 
     Electrical and Computer Engineering, University of Cincinnati,           
     June 1991.

 (2) J. Roy, R. Dutta, N. Kumar, and Ranga Vemuri, 
     "DSS:  A Distributed High-Level Synthesis System", pp. 30,
      invited for publication in IEEE Design and Test of Computers,
      June 1992 (?).

 (3) R. Dutta and Ranga Vemuri, "Distributed Design Space Exploration
     for High-Level Synthesis Systems", pp. 20,
     TM-ECE-DDE-91-20, Oct 1991.

 (4) J. Roy and Ranga Vemuri, "A Parallel Algorithm for Register
     Optimization", pp. 22, TM-ECE-DDE-91-21, (revised) Oct 1991.

 (5) N. Kumar, "A Parallel Algorithm for Finite-State Machine 
     Verification", pp. 18, TM-ECE-DDE-91-22, Oct 1991.

 (6) Ranga Vemuri, P. Mamtora, and J. Roy, "Benchmarks for
     High-Level Synthesis", pp. 10+9 TM-ECE-DDE-91-11, June 1991.

 (7) J. Roy, N. Kumar, R. Dutta, P. Mamtora and Ranga Vemuri,"VSS: It's
     Organization and Structure", pp. 5, TM-ECE-DDE-91-15, June 1991.

 (8) Jay Roy and Ranga Vemuri, 
     "Guide to the VHDL Synthesis System, VSS"
     pp. 23, TM-ECE-DDE-91-21, June 1991.

 (9) J. Roy and Ranga Vemuri, "Appropriate Usage of VHDL : The Synthesis
     Point of View", TM-ECE-DDE-89-08, pp. 50, December 1989. 
     (under revision)

(10) J. Roy, "The VSS Intermediate Format", pp. 13, 
     TM-ECE-DDE-91-16, March 91.

(11) N. Kumar and G. Kamat, "The VHDL Output of the DSS Synthesis System
     and Its Mapping to L", TM-ECE-DDE-91-17, pp. 19, June 1991.

(12) Ning Ren and Ranga Vemuri, "Distribution of Esim on a Network of 
     Workstations", TM-ECE-DDE-91-19, pp. 25, June 1991. 

(13) Ning Ren and Ranga Vemuri, "Distributed VHDL Simulation on
     a Network of Workstations", TM-ECE-DDE-91-23, (in preparation).

(14) P. Mamtora, "Register-Level Component Generators", pp. 22,
    TM-ECE-DDE-91-13, June 1991.

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(V) TERMS AND CONDITIONS :

All the benchmarks and related software can be used by anyone 
on an "as is", "no commitments or guarantees attached" basis. 
We will, however, be glad, as our time permits, to
assist interested parties in any way possible and as promptly as
possible. However, we should not be hold responsible for any problems 
related to the benchmarks or our software.

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(VI) BACKGROUND AND ACKNOWLEDGMENTS

Distributed Synthesis Systems Research at the Laboratory for Digital 
Design Environment is sponsored in part by the Defense Advanced Research 
Projects Agency under order no. 7056 monitored by the Federal Bureau of 
Investigation under contract no. J-FBI-89-094, the Wright-Patterson 
Air-Force Base (ELED), and the University of Cincinnati Research Council.
The research team consists of Jay Roy, Nand Kumar, Paddy Mamtora,
Jeff Kehl, Mike Pelletier (presently with DEC), Rajiv Dutta (presently 
with LSI Logic), Ning Ren, and Praveen Sinha and is lead by 
Prof. Ranga Vemuri.  If you wish, you may reach any of these persons at 

Laboratory for Digital Design Environments
Department of Electrical and Computer Engineering
805C Rhodes Hall, Mail Location 30
University of Cincinnati
Cincinnati, Ohio 45221-0030

Ph: (513)-556-4784.

If you wish to send an e-mail send it to "ddel@thor.ece.uc.edu" 
or to "ranga@uceng.uc.edu" (Prof. Ranga Vemuri).

Paddy Mamtora was instrumental in gathering the textual or non-VHDL 
descriptions of these machines from various sources. The benchmarks 
themselves were originally written by the following persons with 
guidance from the above research team, most notably Ranga Vemuri 
and Jay Roy.  At the time all these persons were students in a 
graduate level course taught by Ranga Vemuri.

Ricci Heishman, David Hollinden, John Krautheim, Tim McBrayer, 
Praveen Sinha, S. Panchumarti, Mich Horton, Sandeep Aji, Rajiv Dutta,
Srini Ranganarajan, Raghu Vutukuru, Guruprasad, S. Datta, 
S. Bangalore, P. Subba Rao, Nand Kumar, Ranjan Prasad, 
Paul Joslin and Jay Roy.
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