This directory contains material from the Vsim project at the
University of Adelaide.  For further information, contact Peter
Ashenden (petera@cs.adelaide.edu.au).

See also the Technical Report pub/CS-TR-93-01.ps.Z (compressed
postscript).


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benchmarks.tar.Z - compressed tar archive of benchmarks directory:

The structural aspects of the VHDL models have been "manually"
elaborated, since the prototype simulator that was developed didn't
implement component instantiation.

benchmarks/reg4 - a small example circuit taken from the VHDL
Cookbook, consisting of a 4 bit register implemented with D-flipflops.

benchmarks/dlx - a behavioural model of the DLX processor (described
in Hennessy & Patterson "Computer Architecture: a Quantitative
Approach"), together with a clock driver, memory and bus monitor.

Benchmarks/multiplier - two models of a 32-bit shift-and-add
multiplier: a RTL level model and a low-level model.  In the low-level
model, each register is implemented as a bunch of flipflips, the adder
is implemented as a bunch of full-adders, and the control section is a
simple behavioural state sequencer.

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