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    	AnaVHDL: A MIXED-SIGNAL CIRCUIT-LEVEL VHDL SIMULATOR

		Center for Digital Systems Engineering
	      Dept. of Electrical & Computer Engineering
		       University of Cincinnati
		          Cincinnati OH 45221

    (C) University of Cincinnati, 1993           All Rights Reserved
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Users Guide
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Introduction
------------

The AnaVHDL simulator is VHDL simulation extended with VHDL packages
to simulate analog circuits described in the SPICE 2G6 format.  The
full VHDL digital simulation capablility is available, and all
non-dependent passive components and MOS transistor (both level 1 and
2) are available. 

Approach
--------

The designer partitions the mixed-signal circuit into analog circuits
and digital circuits.  The only restriction is that analog circuits
cannot directly interface with each other.  That is, an analog output
cannot also be an input of another analog circuit.  Each analog
circuit is then coded as a separate SPICE file.  The digital circuits
are all coded in VHDL in the standard way.  The designer then inserts
a call to the D2A and A2D type transformation functions at all
interfaces between analog and digital circuits to convert current or
voltage waveforms to discrete digital levels.

Procedure
---------

To create and run a mixed-signal simulation (using the MCC VHDL simulator):

	1. Copy all files from the src directory to your working directory.

	2. Put the SPICE descriptions of the analog circuits in separate
    	    files with the specific names "INPUT.TEXTIO1",
    	    INPUT.TEXTIO2"...

    	3. Create your VHDL description including "USE" references to
    	    packages cimpute_pack.vhdl, io_pack.vhdl, interface_pack.vhdl,
    	    A2D.vhdl, and D2A.vhdl.  Insert calls to A2D and D2A as
    	    appropriate to interface analog and digital signals.  See
    	    the examples for more detail on creating your VHDL code.

	4. Analyze all the VHDL files on MCC VHDL simulator using the command:

	     va -v compute_pack.vhdl io_pack.vhdl interface_pack.vhdl 
		   A2D.vhdl D2A.vhdl <file1> <file2> ... <top_file>

	     where-

    		file1, file2...top_file : The vhdl heirarchical VHDL 
					  descriptions of digital circuits 
					  under test.  
		v			: Creates object files for use
    	    	    	    	    	  by the MCC VIDEO debugger.

	5. Simulate the circuit using the following MCC simulator command :

	     vs -R res work.entity

    	     where-

		R res	: Res is the resolution limit for simulation which is
    	    	    	  one of fs, ps, ns, us, ms, ...

    	        work.entity: The name of the top-level library file to
    	    	    	  be simulated.  "entity" is the top level
    	    	    	  entity name.


    Note : There are Makefiles in the directory "examples". Users can use this 
	   as a template to create their own makefiles.

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