*-----------------------------------------------------------------------------*
*        Welcome to VHDL Repository in Unversity of Cincinnati.  The same     *
*     repository was installed on uceng.uc.edu and thor.ece.uc.edu before,    *
*     and is now moved to this ftp anonymous site (ftp.ececs.uc.edu).         *
*                                                                             *
*        If you have any question about this repository, please send your     *
*     email message to smohanty@ececs.uc.edu.                                 *
*                                                                             *
*        For technical problems concerning this ftp site, please contact      *
*     userhelp@ececs.uc.edu.                                                  *
*                                                                             *
*        Contributions and suggestions are highly appreciated.                *
*                                                                             *
*        Please read the "00index" file for a complete list of files.         *
*-----------------------------------------------------------------------------*

Some of the stuff here are:

00README: Readme file for the VHDL archive at thor.ece.uc.edu.

00Index:  Index file for the VHDL archive at thor.ece.uc.edu.

*********** NEW **********

Docs:     VHDL, Verilog, Synthesis and Misc documents related to
	  the scope of this site will be placed in this Directory.
	  Currently it contains Quick Reference Cards for VHDL,
	  Verilog and 1164 packages from Janick Bergeron & Qualis
	  Design Corporation.

**************************

/analog:  A mix-mode simulation package with capability of using
	  SPICE and VHDL developed in Univ. of Cincinnati.  This 
	  directory contains source, documentation, and examples 
          files for the AnaVHDL mixed-signal circuit-level simulator. 
	  A compressed tar file is also provided for the convienent 
	  transfer of all directories.

*********** NEW **********

/compose:  Compose Architecture VHDL files from the University of Cincinnati.
	   Developed by Venkatram Krishnaswamy and Prof. Philip A. Wilsey
	   at the University of Cincinnati.

**************************

/cookbook: Peter Ashenden's VHDL Cookbook.

/februno:  Tar file of Frank E. Bruno's Project materials from Tufts 
	   University.

/general: 
           A complete user's guide for how to use the VHDL repositoty
	   and the VHDL-SW mailing list. Please note that the repository
           is now moved to thor.ece.uc.edu. So anything regarding to
           downloading of the files should change the address from
           `uceng.uc.edu' to `thor.ece.uc.edu' or 129.137.8.118. 

/models  :
/models/Vsim: Vsim project material from the University of Adelaide, Australia.
/models/armstrong: A tar file which contains a lib for VHDL models.
/models/dlx:  Peter Ashenden's VHDL model of the dlx microprocessor.
/models/recursive: Peter Ashenden's VHDL Recursive model.

/packages: VHDL Random number package written by G. Swaminathan from 
	   Univ of Virginia.

************ NEW ************

/petri   : Tar file of VHDL design libraries supporting the construction 
           of Petri Nets. Developed by Sidhartha Mohanty and Dr. Philip 
	   A. Wilsey at the University of Cincinnati.  

/queue   : Tar file of VHDL design libraries supporting the construction
	   of Queueing models.  Developed by Sidhartha Mohanty at the
	   University of Cincinnati.

*****************************

************ NEW ************

/synthesis_benchmarks : The University of Cincinnati synthesis benchmarks 
			directory.  All the benchmarks are written using 
			a behavioral subset of VHDL and are simulatable. 
			Maintained by the Digital Design Environments Lab,
			ddel@thor.ece.uc.edu.

*****************************

************ NEW ************

/tools   : Some tools used in VHDL environment.

*****************************
/validation: A test suite for 1076-1987 IEEE std VHDL language.

/vhdl-93:  VHDL-93 BNF.