Peter J. Ashenden and Philip A. Wilsey
February 1999
As the complexity of integrated hardware and software systems increases, system-level design languages are becoming increasingly important. Such languages rely on abstraction as the key to managing complexity. Designers focus first on the abstract properties of a system in various domains and devise a systems architecture that will satisfy the requirements placed on the system. The domains under consideration include behaviour, structure, performance, physical arrangement and packaging, power consumption, thermal, cost, and so on. In each domain, abstraction is used to focus on the major aspects of the system and minor detail is ignored. Judicious choice of abstractions makes architectural design and analysis tractable, and aids subsequent partitioning and refinement of the system design.
Hardware description languages focus on describing systems in the behavioural and structural domains. However, due to their origin as languages for hardware design, they frequently do not include strong capabilities for abstracting over data and for describing complex interactions. For example, in Verilog, data types are closely bound to their binary representation, and signalling between modules includes aspects of electrical implementation. VHDL, on the other hand, allows more abstract expression of data, and its type system is similar to that of conventional programming languages. However, its signalling features are still closely bound to electrical implementation.
The SUAVE (SAVANT and University of Adelaide VHDL Extensions) project commenced during Ashenden's study leave at the University of Cincinnati in 1997. The project formed one of the tasks of the SAVANT project, funded by the US Air Force. The aim of the SUAVE project is to extend VHDL to improve its support for system-level modeling. VHDL was chosed as the basis for extension as it already has core features to support engienering of complex systems by large design teams, and is widely used for high-level and register-transfer-level design and for design of complex test benches. The SUAVE extensions to VHDL are based on the requirement in a system-level description language for:
During 1997, Ashenden surveyed previous proposals for object-oriented extensions to VHDL and system-level design languages used for software systems. The survey revealed that previous proposals were not founded on good language design principles, and lacked analysis of language design issues and user requirements. The survey work lead to design objectives for extensions to VHDL. Design objectives motivating specific new language features, included:
Further design objectives constraining the design of extensions were:
Based on the design objectives, Ashenden and Wilsey developed initial specifications for language extensions. The extensions for abstraction of data are based on aspects of the Ada-95 programming language: the "programming by extension" mechanisms for object-oriented programming are adopted largely unchanged, and the genericity features are included in a form that integrates with VHDL's existing genericity features.
Extensions for abstraction of communication and concurrency were also developed. Abstract communication takes the form of asynchronous message passing on communication channels. Abstract concurrency takes the form of process declarations that may be statically or dynamically instantiated.
Extensions for description of interface protocols are yet to be developed within the SUAVE project. The value of separately specifying interface protocols in a system-level design language has been demonstrated by ICL as part of the SuperVise design methodology. However, ICL's extensions to VHDL are poorly defined, and do not integrate well with VHDL's existing language features.
The aim of the SUAVE Project is to develop and demonstrate well-founded extensions to VHDL to support system-level modeling. Ongoing work in the project will
The development of well-founded extensions to VHDL for system-level modeling is of direct economic value to the microelectronics and computer-systems design industries. The extended version of VHDL will enable significant improvement in the design flow for electronic and computer-based systems. Currently, design automation for such systems commences at the register transfer level. System-level design is usually performed using ad hoc methods, or using tools that do not integrate with subsequent stages of the design flow. Previous work (e.g., in the RASSP Program) has demonstrated the potential benefit of using VHDL in the early stages of the design flow.
The extended version of VHDL will ease introduction of design automation at the early stages of the design flow. This will allow designers to describe and verify system architectures and to explore alternative architectures before partitioning into hardware and software components. Use of simulation and other verification tools at this level reduces the impact, and hence the cost, of design defects. Furthermore, use of a single language for system-level and lower-level design makes regression testing and refinement verification more tractable and less costly. Ultimately, the benefit of using the extended version of VHDL early in the design flow is a more reliable design process and reduced time to market. Designers will be able to focus their time and effort on the early, strategic design decisions, and rely more on design automation tools to perform synthesis and optimization at lower levels of abstraction.
The availability of quantitative data on implementation costs for the extensions will assist EDA tool vendors in managing adoption of the extensions. Thus the production of the data will facilitate transfer of the language extensions to industry.
The importance of developing a suitable system-level design language is emphasised by the EDA Industry Council. In its EDA Industry Standards Roadmap, the the development of standards to support system-level design is identified as a high priority in the near term. The Industry Council has formed the System Level Design Language (SLDL) Committee to determine requirements and to evaluate candidate languages for adoption as industry standards.
It is expected that the costs of implementing the SUAVE extensions will not be great, compared to the overall cost of developing EDA tools. Furthermore, implementation of the extensions will have negligible impact on the runtime performance and synthesizability of existing models. Thus the benefits of the extensions, when weighed against their implementation costs, will make the extensions attractive to system-level designers.
It is expected that the proposed research on language extensions for describing interface protocols and their refinement will result in new language features that integrate well with existing features and the SUAVE extensions, that are well defined, and that support automatic synthesis and formal analysis.
The work in the SUAVE project is being done in the context of the international EDA standards
community. Ashenden and Wilsey are both active members of the IEEE Design Automation
Standards Committee (DASC), the body responsible for development and maintenance of the
VHDL and related standards. The IEEE VHDL standards are also adopted as international
standards by the IEC. The SUAVE extensions are under consideration for adoption by working
groups of the DASC. It is expected that the SUAVE extensions will strongly influence the
development of VHDL in the 2003 re-standardization round, and the development of related
standards supporting object-oriented and system-level modeling.