The Student's Guide to VHDL

Peter J. Ashenden

This is a list of chapters and appendices in The Student's Guide to VHDL. Follow the links to a more detailed listing of topics.

Preface

Fundamental Concepts

Scalar Data Types and Operations

Sequential Statements

Composite Data Types and Operations

Basic Modeling Constructs

Subprograms

Packages and Use Clauses

Resolved Signals

Generic Constants

Components and Configurations

The Predefined Package Standard

IEEE Standard 1164

VHDL Syntax

Differences Between VHDL-87 and VHDL-93

Answers to Exercises

References

Index

Detailed Table of Contents

1.1 Modeling Digital Systems

1.2 Domains and Levels of Modeling

1.3 Modeling Languages

1.4 VHDL Modeling Concepts

Elements of Behavior

Elements of Structure

Mixed Structural and Behavioral Models

Test Benches

Analysis, Elaboration and Execution

1.5 Learning a New Language: Lexical Elements and Syntax

Lexical Elements

Syntax Descriptions

Exercises

2.1 Constants and Variables

Constant and Variable Declarations

Variable Assignment

2.2 Scalar Types

Type Declarations

Integer Types

Floating-Point Types

Physical Types

Enumeration Types

2.3 Type Classification

Subtypes

Type Qualification

Type Conversion

2.4 Attributes of Scalar Types

2.5 Expressions and Operators

Exercises

3.1 If Statements

3.2 Case Statements

3.3 Null Statements

3.4 Loop Statements

Exit Statements

Next Statements

While Loops

For Loops

Summary of Loop Statements

3.5 Assertion and Report Statements

Exercises

4.1 Arrays

Multidimensional Arrays

Array Aggregates

Array Attributes

4.2 Unconstrained Array Types

Strings

Bit Vectors

Standard-Logic Arrays

String and Bit-String Literals

Unconstrained Array Ports

4.3 Array Operations and Referencing

Array Slices

Array Type Conversions

4.4 Records

Record Aggregates

Exercises

5.1 Entity Declarations

5.2 Architecture Bodies

Concurrent Statements

Signal Declarations

5.3 Behavioral Descriptions

Signal Assignment

Signal Attributes

Wait Statements

Delta Delays

Transport and Inertial Delay Mechanisms

Process Statements

Concurrent Signal Assignment Statements

Concurrent Assertion Statements

Entities and Passive Processes

5.4 Structural Descriptions

Component Instantiation and Port Maps

5.5 Design Processing

Analysis

Design Libraries, Library Clauses and Use Clauses

Elaboration

Execution

Exercises

6.1 Procedures

Return Statement in a Procedure

6.2 Procedure Parameters

Signal Parameters

Default Values

Unconstrained Array Parameters

Summary of Procedure Parameters

6.3 Concurrent Procedure Call Statements

6.4 Functions

Functional Modeling

Pure and Impure Functions

The Function Now

6.5 Overloading

Overloading Operator Symbols

6.6 Visibility of Declarations

Exercises

7.1 Package Declarations

Subprograms in Package Declarations

Constants in Package Declarations

7.2 Package Bodies

7.3 Use Clauses

7.4 The Predefined Package Standard

Exercises

8.1 Basic Resolved Signals

Composite Resolved Subtypes

Summary of Resolved Subtypes

8.2 IEEE Std_Logic_1164 Resolved Subtypes

8.3 Resolved Signals and Ports

Resolved Ports

Driving Value Attribute

8.4 Resolved Signal Parameters

Exercises

9.1 Parameterizing Behavior

9.2 Parameterizing Structure

Exercises

10.1 Components

Component Declarations

Component Instantiation

Packaging Components

10.2 Configuring Component Instances

Basic Configuration Declarations

Configuring Multiple Levels of Hierarchy

Direct Instantiation of Configured Entities

Generic and Port Maps in Configurations

Deferred Component Binding

Exercises

Index to Syntax Rules

C.1 Design File

C.2 Library Unit Declarations

C.3 Declarations and Specifications

C.4 Type Definitions

C.5 Concurrent Statements

C.6 Sequential Statements

C.7 Interfaces and Associations

C.8 Expressions

Lexical Differences

Syntactic Differences

Semantic Differences

Differences in the Standard Environment

VHDL-93 Facilities Not in VHDL-87