Peter J. Ashenden
VHDL is a language for describing digital electronic systems. VHDL allows for the efficient design and simulation of a hardware system before it is actually manufactured—a vital, efficient step in the system design process. This new, condensed version of The Designer's Guide to VHDL provides a tutorial introduction to the fundamental modeling features of VHDL and shows how the features are used for the design of digital systems.
"Engineering students who need to master VHDL...will find Ashenden's guide to be indispensable—and written in an accessible style rarely found in engineering texts."
Offering the same clear, asseccible style as the designer's guide, The Student's Guide to VHDL is designed as a main text for introductory VHDL courses and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.
Peter J. Ashenden is a professor of computer science and computer engineering at the
University of Adelaide, Australia. He actively researches design methods and computer-aided
design tools for VHDL, and he is a participant in the IEEE working groups that develop VHDL
and related standards. He is the author of The VHDL Cookbook and The Designer's Guide to
VHDL (Morgan Kaufmann).