Peter Ashenden
Department of Computer Science, University of Adelaide, Australia
Ali Moini
Department of Electrical and Electronic Engineering, University of Adelaide, Australia
October 1998
The project aims to develop a suite of synthesis techniques for translating behavioural analog/mixed-signal models into component-level implementations, and to develop analog/mixed-signal behavioural modeling methodologies that enable models to be synthesized into component-level implementations. Improvement of current design techniques is required for the semiconductor industry to meet the challenges of “system on a chip” design. Such systems will increasingly include analog components and interfaces. The proposed research will form the basis for product development to meet these challenges.
Funding of approximately $AU20,000 per annum for a Postgraduate Scholarship will be requested for this project as part of a proposal to the ARC Strategic Partnerships with Industry - Research and Training (SPIRT) Scheme for 2000-2002.
The semiconductor industry has seen continued growth for some time, based on continuous improvement in the underlying silicon IC technology. Most of the growth has been in the area of digital VLSI and computer-based systems. However, the recent development of "system on a chip" integration and the growth of the telecommunications industry has lead to the increased importance of integrating analog and RF functionality.
Successful exploitation of the underlying technology depends on design capability, supported by electronic design automation (EDA) tools. Currently, digital systems are designed by developing models in a hardware description language (HDL), such as VHDL or Verilog, both standardised by the IEEE. The models are then simulated to verify correct functionality, and then synthesis tools are used to refine the models to gate-level netlists. The use of synthesis tools is pivotal, as it raises the level of abstraction at which design is performed beyond the gate level to the register transfer level (RTL) or higher. This makes de-sign of complex systems tractable.
Design of analog circuits likewise relies on modeling and simulation, however, the HDL support for expressing analog behaviour is much less mature. Until recently, most analog designs were simulated using SPICE, relying on predefined or externally-provided libraries of component models. Currently, IEEE working groups are defining analog/mixed-signal extensions to HDLs. These will allow expression of the required analog behaviour in equational form, rather than as interconnections of library components, and consequently simulation and verification of the behaviour at a higher level of abstraction.
The analog/mixed-signal extension to VHDL (VHDL-AMS) allows analog behaviour to be described in terms of differential and algebraic equations (DAEs). An analog model may include terminals at which Kirchhoff conservation laws apply (conservative systems), and analog quantities (signal flow systems). A model includes simultaneous statements, which are equations that relate quantities and aspects of terminals using arithmetic, differential and integral operators. Mixed-signal modeling is supported by threshold detectors in the analog-to-digital direction, and by slew and ramp generators in the digital-to-analog direction. In a simulation environment, an analog solver is invoked to determine solutions for the DAEs derived from the simultaneous statements and a number of implicit equations.
The analog extensions to Verilog (Verilog-A) are similar. A Verilog module includes ports of electrical or other types, and functional statements describing the behaviour of the module. Mixed-signal modeling is provided by threshold functions and ramp generators. For simulation purposes, often a SPICE-based simulator is used to solve the DAEs.
The proposed research has two primary aims:
Whereas digital design is supported by a mature synthesis technology, there is no similar support for synthesis of analog designs. What little analog synthesis technology is available is based on parameterizable application-specific component generators. This parallels the state of digital synthesis in the early 1980s. Research into analog synthesis techniques from behavioural descriptions is in its infancy. The proposed research aims to contribute to this important developing field by deriving techniques for analog synthesis that may be embodied in future analog synthesis tools.
As in the field of digital synthesis, not all behavioural analog/mixed-signal descriptions that can be expressed in an HDL will be synthesizable. The proposed research aims to de-termine which language features, when used in prescribed ways, will lead to models that can be synthesized. The proposed research will develop a set of modeling guidelines for using VHDL-AMS and Verilog-AMS to write synthesizable models.
The current lack of synthesis tools means that engineers must manually refine behavioural analog/mixed-signal models into component-level implementations. They must then re-simulate and compare with previous simulation results to verify correct refinement of behaviour. Were analog synthesis tools available, this burden would be removed, and the analog design flow would more closely mirror the digital design flow.
The Semiconductor Industry Association (SIA) has identified analog/mixed-signal design as a difficult challenge that must be met for continued success of the industry. In its National Technology Roadmap, it suggests that
… new design methodologies need to be developed to support tight coupling of analysis, synthesis, and (re)specification activities across multiple levels of representation. These needs apply equally to the design of digital, mixed signal, and analog systems.
The timetable proposed in the Roadmap requires basic research to be done by end-2002 in preparation for product development to start in 2003, followed by product deployment in subsequent years. The timetable for the research proposed in this project is in accord with the SIA Roadmap.
The proposed research will form the basis for product development by the Industry Partner. The latter already has a strong presence in EDA industry, both as a tool user and tool developer. Products based on the outcomes of the proposed research will enable the Industry Part-ner to maintain its competitiveness in a growing sector of the semiconductor industry.
The analog/mixed-signal extensions to both VHDL and Verilog are based on the theory of differential and algebraic equations (DAEs). The research to be undertaken by the requested APAI scholar will initially involve a review of the theoretical basis, and a survey of related research on synthesis of analog circuits from DAE-based models. Next, methods will be devised for synthesizing analog circuits, based on parameterized library components, from a suitable class of DAE models. The class of DAE models identified will form the basis for characterizing VHDL-AMS and Verilog-AMS models as synthesizable using the techniques devised.
The synthesis techniques devised will be incorporated into a prototype synthesis tool for Verilog-AMS. The Industry Partner will provide the framework for the synthesis tool, based on their Verilog-AMS simulation tools. A prototype component library will also be developed based on their analog semiconductor process.
The synthesizable HDL subset and the synthesis techniques will be demonstrated by means of a small number of case-study analog/mixed-signal designs. The Industry Partner will advise on choice of the case-study designs, and the design work will be undertaken by Honours Engineering students at the University of Adelaide.
The first supervisor has been actively involved in development of HDL language standards within the IEEE since 1990. In particular, he is a member of the balloting body reviewing the Draft Standard Language Reference Manual for the VHDL-AMS extensions. He is also author of two leading textbooks on VHDL, and has had experience in implementing compilation and parallel simulation tools for VHDL.
The second supervisor has been actively involved in the design of analog and mixed-signal VLSI chips, in particular smart vision chips. He is currently working on the design of smart imagers, and devising analog behavioural modeling for the design of such chips.
Both supervisors have had experience in supervising students working on research projects, resulting in papers published in journals and conference proceedings.
The first supervisor will advise the APAI scholar on technical aspects of design flow, HDL-based modeling methodology, HDL semantics, and EDA tool development. The second supervisor will advise the APAI scholar on technical aspects of analog modeling, analog component design, and analog synthesis. The supervisors will jointly supervise the non-technical aspects of the APAI scholar’s PhD candidature.
The APAI scholar will undertake the proposed research as described in the section “Research plan, methods and techniques,” with the exception of the development of case-study designs. The APAI scholar will enrol as a PhD student at The University of Adelaide.
The Industry Partner will advise on design of analog library components using the Industry Partner’s semiconductor process, and on extension of Industry Partner’s Verilog-AMS tools to incorporate analog synthesis techniques. The Industry Partner will make an expert staff member available for these purposes for one day per month.
In the final year of the proposed research, Honours Engineering students will undertake case-study design projects to demonstrate use of the synthesizable Verilog-AMS subset and the prototype synthesis tools.
Peter Ashenden
Dept. Computer Science, University of Adelaide, SA 5005, Australia
Phone: +61 8 8303 4477
Fax: +61 8 8303 4366
Email: petera@cs.adelaide.edu.au