Peter Ashenden
Department of Computer Science, University of Adelaide, Australia
February 1999
This project involves extending the SAVANT compiler and simulator to support the SUAVE language extensions. A number of subprojects are available, each involving implementation of different language features in the compiler and simulaotr run-time support. The work will involve collaboration with developers at Adelaide and the University of Cincinnati, USA. No hardware design background is assumed.
The SUAVE project has already commenced implementation of a compiler for the extensions for object-oriented data modeling and genericity. This tool is based on the "scram" analyzer for standard VHDL, forming part of the SAVANT tool suite under development at the University of Cincinnati. Scram uses freely available compiler-generator tools (flex and PCCTS) to build a parser. Actions routines in the grammar file generate an extensible intermediate form using the AIRE abstract syntax classes. Tree-processing methods perform static semantic analysis and generate C++ code to be compiled and linked with the TyVIS distributed simulation kernel.
Work to date has included implementation of most of the grammar and static semantic checking in the compiler, and some code generation for the object-oriented language extensions. The subprojects described below involve completing the implementation of the static semantic checking and code-generation methods for the SUAVE extensions, and providing run-time support for the extensions in the TyVIS kernel. The resulting tool suite will enable full syntactic and semantic analysis and simulation of models written in the extended language.
SUAVE adopts from Ada-95 the notions of private types and private parts in packages. Some modifications to the Ada language features are needed to integrate the features into the VHDL semantic framework. This subproject will mainly involve completion of static semantic checking.
SUAVE also adopts from Ada-95 the notions of generic packages and generic subprograms. These language features allow definition of parametric-polymorphic data types, and in particular, generic container types. Such types will find application in complex test-bench software for hardware design and in high-level hardware description.
This subproject will involve developing static semantic checking and code generation for generic packages and subprograms. The code generation work will involve generating code to perform instantiation of generic units when a SUAVE model is elaborated prior to simulation.
SUAVE extends the notion of generics, allowing design entities to have formal generic types. (A design entity represents the interface and implementation of a hardware unit, and can be multiply instantiated in a larger design.) Type-parameterized design entities will affort greater opportunity for design reuse than are currently available.
This subproject will involve developing static semantic checking and code generation for generic blocks, components and entities. The code generation work will involve generating code to perform instantiation of generic units when a SUAVE model is elaborated prior to simulation.
Currently in VHDL, processes are written as static non-instantiable concurrent statements. SUAVE extends the process model by allowing processes to be declared as instantiable units. They can be either statically instantiated when a model is elaborated, or can be dynamically instantiated as a model executes. Processes can also be generic, with actual generic types provided upon instantiation.
This subproject will involve developing static semantic checking and code generation for process declarations and instantiations. The code generation work will involve generating code to perform both static and dynamic instantiation. The simulator runtime support will also have to be extended to handle dynamically instantiated processes.
Currently in VHDL, processes communicate via signals, which are a relatively low-level abstraction of electrical wires. When designers model systems at a high-level of abstraction, they would prefer to ignore low-level details of communication, such as propagation delays, drive contention, and synchronization using hand-shaking or clocked protocols. SUAVE provides a more abstract form of communication based on channels and message passing, similar to the facilities provided in CSP and its derivative OCCAM.
This subproject will involve implementing all aspects of channels and message passing, including grammar specification, static semantic checking, code generation, and run-time support in TyVIS and Warped.
Peter Ashenden
Dept. Computer Science, University of Adelaide, SA 5005, Australia
Phone: +61 8 8303 4477
Fax: +61 8 8303 4366
Email: petera@cs.adelaide.edu.au