Peter J. Ashenden
The source code and test benches for examples are available on this server. There are two versions, a Unix version with LF line terminators (LF) and an MSDOS version with CR/LF line terminators. For each version, there is a separate directory for each chapter. Each directory contains an index file, called index_nn , that lists the VHDL design units contained in each source file. (The digits nn are the number of the chapter.) The source files for most chapters are named as follows:
The exceptions to this naming scheme are the files for the case study chapters (Chapters 6, 10, 15 and 19), since some of the design units are divided across several figures in the book. For these chapters, the files names are based on the names of the design units.
Each chapter directory also contains an archive of all of the source files for that chapter. In the Unix version the archive is in compressed tar format. In the MSDOS version, the archive is in ZIP format.
Each version directory also contains an archive of all of the source files for the whole book, useful if you want to retrieve everything at once.
In addition to the source for each chapter, there is a utilities directory, containing a test generator utility package. Several of the test benches use procedures in this package to generate test stimuli.
The source code has all been tested using the Model Technology Inc V-System/Workstation analyzer and simulator. I am most grateful to the people at MTI for the use of the tools and for their support.
If you have comments, please send me email at petera@cs.adelaide.edu.au. Thanks.