The Designer's Guide to VHDL

Suggestions for Exercises

Coming up with ideas for design exercises can be quite a difficult task, as I found when developing the exercises for the book. If you are learning VHDL, this page may give you some ideas for projects to practice VHDL design skills. If you are a VHDL instructor, I hope this page will provide some inspiration for exercises for your students.

Combinatorial Logic

• basic logic gates: and, or, inverter, nand, nor, xor, xnor
• simple Boolean functions
• multiplexers: 2-input, n-input
• decoders
• priority encoder
• majority function
• transmission gates: unidirectional, bidirectional
• open-drain inverters/buffers
• tristate buffers: unidirectional, bidirectional
• ripple-carry adder
• adder/subtracter: mode input '0' = add, '1' = subtract
• carry-look-ahead adder
• Manchester carry adder: uses precharged carry-look-ahead chain, uses register-kind signals
• parity generator
• binary magnitude comparator
• address decoder (e.g., to generate chip selects)
• ALU
• barrel shifter
• Muller-C element
• dual-rail self-timed asynchronous logic elements
• arbiter (including metastability detection)

Storage Elements

• transparent latch, register
• edge-triggered flipflop, register
• JK flipflop
• static RAM (SRAM)
• dynamic RAM (DRAM)
• content addressable memory (CAM)
• cache tag RAM

Counters

• ripple or synchronous
• up, down, up/down
• binary, BCD
• with/without terminal count, reset, parallel load

Shift Registers

• serial-in/parallel-out
• parallel-in/serial-out

Subprograms and Packages

• maximum and minimum functions
• package of overloaded arithmetic operators for standard-logic vectors
• package of component declarations for logic gates, etc.
• package of procedures for timing checks, entities with passive procedure calls to timing check procedures
• test generator procedure with a bit vector or standard logic vector signal parameter, generates all possible combinations of stimulus vectors and assigns them to the parameter at intervals specified by a second parameter
• conversion functions: real to bit_vector in IEEE floating-point format

Generated Structures

• ripple carry adder generated from full-adder cells
• carry-look-ahead (CLA) adder generated from 4-bit CLA adders and 4-bit CLA expansion cells (such as 74xx182)
• parity tree: recursive model or iteratively generated model
• parallel array multiplier: iteratively generated model

Miscellaneous

• serial adder: shift operands through a full-adder, and use a D-flipflop for intermediate carries
• serial adder/subtracter: mode input '0' = add, '1' = subtract
• multiplier, divider: based on descriptions in Appendix A of Hennessy & Patterson, Computer Architecture: A Quantitative Approach.
• FIFO: fall-through implementation, circular buffer implementation
• LIFO stack: register file and up/down counter
• programmable logic devices: models for specific organizations, programmed from a file (simple fuse map, or JEDEC) or a generic constant
• paged virtual memory management unit: includes address translation, TLB, page table walker
• packet routing switch for multicomputer interconnection network
• hardwired or microprogrammed control section for the DLX CPU in Chapter 15
• pipelined CPU (e.g., the DLX from Chapter 15)
• error correcting code (ECC) generator/checker
• memory system with ECC
• digital stopwatch
• IEEE floating-point multiplier, divider, etc.
• traffic light controller: finite state machine
• greatest common divisor using the following algorithm, implemented with a datapath (ALU, registers, etc.) and control sequencer:

while a != b do

if a > b then a = a - b else b = b - a

• pipelined polynomial evaluator: use the form

f(x) = A0 + x (A1 + x (A2 + ... + x (An-1 + x An) ... ) )

successive x values enter on each clock cycle, each stage multiplies result from previous stage by x and adds its coefficient

• UART
• Parallel I/O port
• bus arbiter: round-robin or priority
• cache memory
• keypad scanner/encoder with debounce
• interrupt control unit for microprocessor
• bus-functional CPU model: reads address/data trace from file and generate bus transactions
• byte-alignment module for CPU bus interface
• microcomputer I/O controllers: e.g., serial I/O, parallel I/O, diskette, SCSI, network interface, DMA
• Synchronous serial comms controller: character-oriented protocol, bit-oriented protocol
• complete microcomputer system
• vending machine controller
• dynamic register using pass transistors and inverters (using register-kind signals)
• types and resolution function for interval logic, gates using interval logic
• asynchronous dataflow arithmetic circuit using integer type for data: use of 'transaction attribute to detect arrival of new value
• household burglar alarm: key-switch or PIN activated, exit delay after enabled, entry delay after being tripped by a sensor
• four-phase handshaking protocol between data source and data sink
• test vector extractor for a test bench: monitors stimulus and response signals connected to dut, writes stream of timestamped vectors to file for use in regression testing a refined model of dut
• serial parity checker using FSM
• serial CRC checker
• pulse-width modulator: 8-bit data in (binary coded data D), master clock in, for each group of 255 master clock cycles, data out is '1' for D cycles, then '0' for 255-D cycles
• gray-code to binary or BCD converter
• 2910 microcontroller
• JTAG boundary scan cell
• limited up/down counter, with loadable upper and lower limit registers, counter loadable from either limit register
• crossbar switches: serial or parallel, unidirectional or bidirectional
• servo position controller for motor driven shaft, sensor on shaft gives current position (e.g., gray-coded, or quadrature-encoded motion), data input gives required position, binary encoded output to DAC gives motor current
• waveform generator: master clock input divided down to get low-phase and high-phase for output waveform, phase durations specified by inputs or register values
• dual-port RAM, including arbiter to enforce mutual exclusion if both ports access same location (allow both to read, but exclusive writes)
• serial I/O RAM
• real-time clock/calendar chip for microcomputer system: don't forget to deal with the possibility that the time may tick over part way through reading successive bytes
• multi-tap delay line: fixed delay, or specified by generic constants
• DRAM controller chip: generates RAS/CAS, multiplexes address bits, handles refresh
• lookup ROM for sine, cosine, etc., initialized using a function
• 74S508, 74S516 sequential multiplier/dividers
• RasterOp function unit
• n-tap FIR filter
• FFT