QUESTION:

I am looking for ways to reduce the area in my design. I am meeting timing very easily, so that is not an issue. What do you recommend?

ANSWER:

1. For DC 98, set an area constraint and use a high effort compile to kick in the new gate composition algorithm. For one pass compiles you have to do "compile -map_effort high", for 2 pass compiles, you can always try a "compile -map_effort high -incremental_map" for the second compile.
2. Choose to enable area optimization at the risk of worsening timing violations on some paths and creating some new timing violations. This is how Design Compiler operated until Design Compiler 98. With Design Compiler 98, TNS (total negative slack) is being used, which means that cell resizing to recover area is not done if the paths are made negative. So, to make Design Compiler 98 work like Design Compiler 97, which did downsize cells in the off-critical path even if it made them negative slack paths, do the following:

        set_max_area 0 -ignore_tns

3. Manage resource selection. The classic example of 'do I use 2 adders and a mux, or do I use 1 adder and 2 muxes?' By default, high-level optimization performs resource allocation and implementation (DesignWare selection) based on timing constraints. To change the default and get Design Compiler to base resource allocation and implementation based on area constraints, do the following before compile:

        dc_shell> set_resource_allocation area_only 
        dc_shell> set_resource_implementation area_only

4. Enable Boolean Optimization. Boolean optimization can use don't care conditions to minimize area. This algorithm performs area optimization only; do not use Boolean optimization for timing-critical designs. Do this before compile:

        dc_shell> compile_new_boolean_structure = true 
        dc_shell> set_structure true -boolean true

5. Boundary Optimization. Tell DC to perform optimization across hierarchical boundaries by using one of the following commands:

        dc_shell> compile -boundary_optimization

or,

        dc_shell> set_boundary_optimization subdesign

Design Compiler will propagate constants, unconnected pins, and complement information. In designs that have many constants, propagation can reduce area.
6. Hierarchy removal. Removing levels of hierarchy by ungrouping gives Design Compiler more freedom to share common terms across the entire design. Ungrouping DesignWare parts can also reduce area. Try compiling larger blocks, with the hierarchy removed for the lower levels.
7. Low effort first pass compile. Do this only if your design is meeting timing. Experiments have shown that a low_effort compile can produce a smaller gate count than for medium and high effort compiles.
8. Do some of your designs contain multipliers followed by adders? How about adder trees? If so, Boa/BRT (Behavioral Optimization of Arithmetic = Boa, Behavioral Retiming = BRT) can help by using CSA trees which essentially replace large CLA adders with CSA adder trees (ripple adders). BRT would be helpful if you have a block that is pipelined, because the BRT algorithm will place the registers at a spot which gives the minimum amount of registers.
9. You might want to try the following variable: compile_sequential_area_recovery = true. When this is set to true, compile remaps the sequential elements in the design to try and recover area. In doing so, compile will not worsen the delay cost of the design. However, the negative slack on violating, but non-critical paths might be worsened. For information about this, do the following:

     dc_shell> man compile_sequential_area_recovery

Here is how you might use this variable when doing a bottom up compile:

     dc_shell> set_max_area 0 -ignore_tns 
     dc_shell> compile_sequential_area_recovery = true

Do the previous for your subblocks, then do the following at the top level:

     dc_shell> compile -incremental_map -map_effort high

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