Frequently Asked Questions And Answers: Part 1
This is a monthly posting to comp.lang.vhdl containing general information. Please send additional information directly to the editor:
edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska)You can also use this form to drop me a short note if your client can handle FORMs.
Corrections and suggestions are appreciated. Thanks for all corrections.
There are three other regular postings: part 2 lists books on VHDL, part 3 lists products & services (PD+commercial), part 4 contains descriptions for a number of terms and phrases used to define VHDL.
The newsgroup comp.lang.vhdl was created in January 1991. It's an international forum to discuss ALL topics related to the language VHDL which is actually defined by the IEEE Standard 1076/87. Included are language problems, tools that only support subsets etc. NOT other languages such as Verilog HDL. This is not strict - if there is the need to discuss information exchange from EDIF to VHDL for example, this is a topic of the group. The group is unmoderated. Please think carefully before posting - it costs a lot of money! (Take a look into your LRM for example - if you still cannot find the answer, post your question, but make sure, that other readers will get the point). A chapter for frequently asked questions about the language will later be added to this regularly posted information - as they appear on the net. If necessary for the amount of information, this posting will possibly be split into separate postings for each chapter.
VHDL-1076 (VHSIC (Very High Speed Integrated Circuits) Hardware Description Language) is an IEEE Standard since 1987. It is "a formal notation intended for use in all phases of the creation of electronic systems. ... it supports the development, verification, synthesis, and testing of hardware designs, the communication of hardware design data ..." [Preface to the IEEE Standard VHDL Language Reference Manual] and especially simulation of hardware descriptions. Additionally VHDL-models are a DoD requirement for vendors.
Today simulation systems and other tools (synthesis, verification and others) based on VHDL are available. The VHDL users community is growing fast. Several international conferences organized by the VHDL Users Groups(s) have been held with relevant interest. Other international conferences address the topic with growing interest as well (Conference on Hardware Description Languages -CHDL-, [European] Design Automation Conference -[Euro]DAC ...).
The basic version of this FAQ was created by Tom Dettmer.
Thanks to Georg Staebner for his work on part 4.
The web site of VHDL International (VI) is at http://www.vhdl.org/vhdl_intl/. The contact address is
VI Membership & Administration, Tel: (408) 492-9806, viadmin@vhdl.orgCurrent Groups on the VHDL International Users Forum System (4 Feb 1997, ver 2.2) - an actual version of this list can be found at http://www.vhdl.org/docs/groups.txt or ftp://vhdl.org/docs/groups.txt (See also http://www.vhdl.org/docs/Groups.html)
Name code-name
------------------------------------------------- ------------
3D TCAD Modeling Interoperability tcad3d
Bay Area MEMS Journal Club bamjc
EIA DAD Advanced Intermediate Rep. with Extensibility aire
EIA DAD DIE ((bare) Die Info Exchange) Format die
EIA DAD IBIS Open Forum (I/O Buffer Info Spec) ibis
EIA DAD Microwave Design Automation Standards microwave
EIA DAD Rule Augmented Interconnect Layout Specification rail
EIA DAD VHDL Commercial Component Model Spec eia567
Free Model Foundation fmf
Free VHDL Products from MTL Systems for Non-commer use mtl
HDL Conference (old IVC and Spring VIUF) hdlcon
IEEE Design Automation Standards Committee dasc
IEEE DASC Chip Hierarchical Design System tech. data WG chdstd
IEEE DASC Circuit Delay and Power Calculation System dpc
IEEE DASC High Performance HDL Simulation WG hpm-sim
IEEE DASC HW/SW Codesign SG codesign
IEEE DASC Open Modeling Forum WG omf
IEEE DASC Standard Delay Format SG sdf
IEEE DASC System Design & Description Language SG sddl
IEEE DASC Timing (VHDL Intiative Towards ASIC Libraries) vital
IEEE DASC VASG ISAC (VHDL) *isac
IEEE DASC Verilog WG 1364
IEEE DASC VHDL Analog Extensions WG analog
IEEE DASC VHDL Library "library ieee;" WG libieee
IEEE DASC VHDL Library - Utility WG libutil
IEEE DASC VHDL Math Package WG math
IEEE DASC VHDL Microwave SG vhdl-mw
IEEE DASC VHDL Object Oriented SG oovhdl
IEEE DASC VHDL Parallel Simulation WG parallel
IEEE DASC VHDL Shared Variable WG svwg
IEEE DASC VHDL Synthesis WG vhdlsynth
IEEE DASC VHDL Test WG vhdl_test
IEEE DASC / SCC20 Waveform and Vector Exchange Std waves
OVI/VI Synthesis Constraints WG scwg
VHDL International (VI) *vi
VHDL International Users' Forum (old VHDL Users' Group) *viuf
VHDL Validation Suite Effort validation
VI Marketing Advisory Committee mac
VI Technical Advisory Committee tac
VIUF Local Chapter - Boston, MA boston_lc
VIUF Local Chapter - Mid-West midwest_lc
VIUF Local Chapter - Phoenix, AZ phoenix_lc
VIUF Local Chapter - Denver, CO rockymnt_lc
VIUF Local Chapter - Sacramento, CA sac_lc
VIUF Local Chapter - San Diego, CA sandiego_lc
VIUF Local Chapter - Silicon Valley (Local Users Group) svlug
VIUF Local Chapter - Southern California socal_lc
* General email exploder / discussion group not available
(note: You can substitute verilog.org, hdlcon.org or eda.org for vhdl.org)
To find out more info about a group, send an email request to:
-info@vhdl.org
To get added to an email exploder and be made aware of the groups
activities, send your email address to:
-request@vhdl.org
To submit a message to an email exploder, email the message to:
@vhdl.org
Most of these groups have active file repositories also (including an
archive of all email discussion traffic). Check either the "pub"
directory for the group of interest.
Teaser packets of information (just to get your feet wet) exist on this
repository for the following groups. (You need to check the home
Internet FTP servers or use Gopher to get the up-to-date and complete files.)
EDIF Technical Center, University of Manchester pub/edif-tc
ISO TC184/SC4/WG4, etc. (STEP Standard) pub/iso10303
ISO TC184/SC4/WG2 - Part Libraries STEP Application pub/iso13584
In addition, there are repositories for the following topics / ad-hoc groups:
Misc. submissions (from VUG/VIUF meetings, etc.) vi/misc
VHDL Users' Group RBBS PC Machine (1988-1991) vi/vug_bbs
Useful public domain tools for UNIX, Macintosh, and pub/tools
PC (DOS and Windows)
You may also join an on-line discussion group via http://www.vhdl.org/vhdl_intl/viis-info.html
The VHDL-Forum for CAD in Europe is the European users group active in VHDL related topics & standardization efforts. VFE is open to all interested participants. Contact:
Andreas Hohl (Chair) SIEMENS, Dept. ZFE IS EA Ref Otto-Hahn-Ring 6 81739 Munich Germany Phone: +49-89-636-41895 Fax: +49-89-636-44950 Email: ah@ztivax.siemens.comMail items of interest to info-vhdl@thor.ece.uc.edu (129.137.8.118)
Mail a request to be added to the group of registered news subscribers to
info-vhdl-request@thor.ece.uc.eduThe purpose of 1076.1 Working Group (WG) is to develop analog extensions to VHDL, i.e. to enhance VHDL such that it can support the description and simulation of circuits that exhibit continuous behavior over time and over amplitude. As of summer 1993 the IEEE Computer Society, through its Standards Activity Board (SAB), has approved the 1076.1 WG under PAR1076.1.
1076.1 Executive Committee
Chair: Jean-Michel Berge
CNET-CNS-CCI
Chemin du Vieux Chene - BP 98
F-38243 Meylan Cedex, France
phone: (+3376) 764-335
fax: (+3376) 903-443
email: berge@cns.cnet.fr
Vice-chair: Ernst Christen
Analogy Inc.
P.O. Box 1669
9205 SW Gemini Drive
Beaverton, OR 97075-1669
USA
phone: (503) 520-2720
fax: (503) 643-3361
email: christen@analogy.com
Secretary: Alain Vachoux
Swiss Federal Institute of Technology
Electronics Laboratories
LEG/C3i - Ecublens
CH-1015 Lausanne
Switzerland
phone: (+4121) 693-6984
fax: (+4121) 693-4663
email: alain.vachoux@leg.de.epfl.ch
1076.1 Mailing List
Reflectors (information to all members of the mailing list):
1076-1@epfl.ch European address
ahdl1076@cadence.com US address
Submit new names to be put on the mailing list to
1076-1-request@epfl.ch
Submit to 1076.1 Executive Committee only:
1076-1-exec@epfl.ch
1076.1 Repositories:
ftp nestor.epfl.ch (or ftp 128.178.50.20)
Material related to the 1076.1 WG is in the directory
pub/vhdl/standards/ieee/1076.1
ftp ftp.uu.net (or ftp 192.48.96.9)
Material related to the 1076.1 WG is in the directory
doc/standards/ieee/1076.1/analog
See http://www.vhdl.org/analog/ for further information.
Standard for VHDL Waveform and Vector Exchange (WAVES). See http://www.vhdl.org/waves/ for further information.
The first (VUG) was transformed into the second (VIUF) in 1991. VIUF is Chaired by Praveen Chawla and is a chapter and thus sponsored by VHDL International (VI). They organize conferences and have some other activities.
WWW: http://server.vhdl.org/viuf/The french (speaking) VHDL Users' Group is actually a 'French-Speaking' due to the presence of Swiss people. (Belgium, Luxemburg and Val d'Aoste people are welcome). Organization is taken in charge by
Roland Airiau - airiau@cns.cnet.fr Jean-Michel Berge - berge@cns.cnet.fr Serge Maginot - serge.maginot@vhdl.org Alain Vachoux - alain.vachoux@leg.de.epfl.chThe first meeting was in Grenoble, November 30th, 1993. There were around 45 people. The meeting was quite good.
maintains the mailing list and manages the group.
Archives:
You can find this FAQ at (USA) http://vhdl.org/comp.lang.vhdl/
archives for this newsgroup: http://kona.ee.pitt.edu/NewsGroupArchives/comp.lang.vhdl/index.html
Updated versions of the various DA-related FAQ's: http://kona.ee.pitt.edu/NewsGroupArchives/NewsGroupArchives.html
There are collections of interesting tidbits from all of the DA Newsgroups at URL: http://kona.ee.pitt.edu/CollectedInformation/NewsgroupHighlights/NewsgroupHighlights.html
Here are some useful links on the web related to VHDL. If you discover an interesting server not mentioned in this list or a link is broken please send a note to the editor.
The following links point to some servers containing "non commercial" VHDL models. Note, there may be some limitations and restrictions concerning the use of this software.
Here are some links to commercial model sites:
For other commercial model vendors see FAQ part 3 products & services.
See also FAQ part 3 products & services for other VHDL vendor sites.
There's not much until today - but I included those questions I've often heard from beginners. If someone feels, that a point should be included, please let me know.
According to IEEE rules every five years a standard has to be reproposed and accepted. This can include changes. Because VHDL is relatively young, the restandardization in 1992 included changes, and it will in 1997.
Changes in VHDL93 include: groups, shared variables, inclusion of foreign models in a VHDL description, operators, support of pulse rejection by a modified delay model, signatures, report statement, basic and extended itentifiers, more syntactic consistency.
This chapter tries to answer some questions about language details which appear more or less regular on the net.
Often users believe, they can use names of libraries /= work by simply inserting a use clause in the source. The analyzer responds with error messages.
Insert a library clause before the use clause and all should work fine (See your LRM or FAQ Part 4 - B.74 for details.
The generate statement (FAQ Part 4 - B.105) is a concurrent statement (FAQ Part 4 - B.44) that contains other concurrent statements. Two forms exist: for and if generate. Example which uses both:
If you have a VHDL'93 compliant tool, it's easier.
The question is often, whether
The '87 LRM is a bit confused as to whether the generate statement forms a declarative region, so it does not make provision for a declarative part in the syntax. However, it was decided that it indeed does form a declarative region (FAQ Part 4 - B.56), so in the '93 LRM we also included the syntax extension necessary for a declarative part. For '87, however, there is no such declarative part. The canonical method is to use an embedded block statement:
Let
Another, related problem is
The following example converts integer (FAQ Part 4 - B.134) to time (FAQ Part 4 - B.182) and time to integer.
The names given to the states (be it X, Z, don't care, even 0 and 1) of an enumeration type (FAQ Part 4 - B.85) have only the meaning brought by the subprograms of the package that defines the type. For example, 0 is 0 only because of the way "and", "or", etc, are written. Z is 'high impedance' and X is 'conflict' only because of the way the package, and particularly the resolution function is written. As for the "don't care", it has no particular meaning for simulation, and the STD_LOGIC package does not provide any semantics for it: it's a normal state.
For example in a case statement like
The file formats for binary files read or written by VHDL are not standardized. However, each simulator should be able to read its own generated binary files. This gives you two choices:
Partially extracted from an article posted by Wolfgang Ecker.
Actually as far as I know, there is only few PD software on VHDL. If YOU know about something, please let us know. See products posting for more detailed information.
Yes. The latest version of the test validation suite is available via anonymous ftp://vhdl.org/vi/validation/vi_suite.tar.Z The current suite covers 36% of VHDL-1987. See http://www.vhdl.org/validation/ for further information.
The working group vote on the draft 1076.1 LRM is closed. The motion to move on to the IEEE ballot has been accepted. The IEEE ballot is currently running.
The 1076.1 study group is maintaining an email bulletin board for distribution of announcements and as a forum for technical discussions. see above (official contacts).
Actually as far as I know no complete list with addresses of all documents exists. In general it's a good idea to look at the
vhdl.org ftp server, fetch the most actual version of the groups list: /docs/groups.txt (see also Official Contacts ... above). The
short names listed there are usually also used as directory names at vhdl.org - just look for /vi/
If someone has a partial or complete list, please send it to the author. I'll incorporate it here, if possible. Here is, what I have:
(See also here)
Of course, there are the other three parts of this FAQ.
Other good starting points are http://www.vhdl.org/docs/groups.txt or section 3. VHDL on the Web.
If other Resources should be listed here, please let me know.