Asia Pacific Technology Roadshow 2011

Date: August 2011 to November 2011 Region: Asia Pacific

Altera's Technology Roadshow will be held in China, India, Korea, Malaysia, and Taiwan. You can get the complete event schedule and seminar abstract below. Register for the event and secure your seat today!

Topics⁽¹⁾ 

• Altera's 28-nm FPGA portfolio
• Backplane design and optimization using 28-nm FPGAs
• Using variable-precision digital signal processing (DSP) blocks in 28-nm FPGAs
• External memory interface implementation using 28-nm FPGAs
• Qsys: 5 reasons to switch from SOPC Builder to Qsys
• Implementing video systems using the Altera^® video framework
• PCI Express^® technology in 28-nm FPGAs
• Optimizing power and performance in 28-nm FPGA designs
• What's new in Quartus^® II software v11.0
• Model-Based Design for Altera FPGAs using HDL code generation

Note:

1. Seminar content will vary between cities.

Event Schedule

Seminars, Topics, and Abstracts

Altera's 28-nm FPGA Portfolio
This presentation shows you how our latest 28-nm portfolio optimizes solutions that addresses your diverse design challenges, meeting unique performance, feature, and power requirements across a wide range of applications. This is done by leveraging the advantages in transceiver technology, product architecture, intellectual property (IP) integration, and process technology.

• 파일명: 01_Altera_28nm_Portfolio_Design_Workshop.pptx (2,865,214 bytes)

Backplane Design and Optimization Using 28-nm FPGAs
This presentation explains the backplane capabilities of Altera's 28-nm FPGAs. See the 10GBASE-KR backplane design kit and get tips on how to successfully implement a 10G backplane design.

• 파일명: 02_backplane_design_and_optimization_using_28nm_FPGAs.pptx (5,202,843 bytes)

Using Variable-Precision DSP Blocks in 28-nm FPGAs
This presentation helps you understand the new variable-precision DSP block and how it can help your designs.

• 파일명: 03_Altera_28nm_DSP_Design_Workshop.pptx (1,231,625 bytes)

External Memory Interface Implementation Using 28-nm FPGAs
This presentation explains external memory interface solutions in Altera 28-nm FPGAs. It features a description of the structure, performance, efficiency, and differences between hard IP and soft IP in 28-nm FPGAs.

• 파일명: 04_Memory_customer_presentation.pptx (1,381,716 bytes)

Qsys: 5 Reasons to Switch from SOPC Builder to Qsys
This presentation shows you how Qsys, the next-generation system integration tool, can take your FPGA design to the next level. Find out how switching to Qsys will help you meet design requirements of higher performance, more IP use, larger feature-rich reference designs, and a more scalable system tool.

• 파일명: 05_Qsys_AP_Tech_Roadshow.pptx (2,051,287 bytes)

Implementing Video Systems Using the Altera Video Framework
This session introduces Altera's video framework and discusses the Video and Image Processing (VIP) Suite of IP cores in detail. Altera's video framework can help you solve your design challenges, such as improving image format conversion quality, offloading DSP processors, and reducing system cost and time to market.

• 파일명: 06_VIP_AP_Tech_Roadshow.pptx (3,768,356 bytes)

PCI Express Technology in 28-nm FPGAs
This presentation describes the hardened PCI Express-based solution in 28-nm FPGAs and how they will benefit user designs.

• 파일명: 07_28nm_PCIe_Overview.pptx (1,538,589 bytes)

Optimizing Power and Performance in 28-nm FPGA Designs
This presentation shows you how Altera's 28-nm FPGAs and Quartus II design software can help you minimize power without sacrificing performance.

• 파일명: 08_optimizing_power_and_performance_in_28nm_FPGAs.pptx (1,399,301 bytes)

What's New in Quartus II Software v11.0
This session showcases what's new in Quartus II software v11.0 and the benefits to your designs. Learn about the improved support for a system integration tool, new device expansion, and debug solutions for faster board bring-up.

• 파일명: 09_QII_AP_Tech_Roadshow.pptx (1,691,598 bytes)

Model-Based Design for Altera FPGAs Using HDL Code Generation
In this session, you will learn how Model-Based Design helps you create FPGA implementations from MATLAB code and Simulink models. Using Simulink HDL Coder, you can rapidly prototype your algorithm on Altera FPGAs, perform optimizations, and create FPGA and ASIC implementations.

• 파일명: 10_MathWorks-2011_Technology_Roadshow.pdf (1,349,210 bytes)