날짜 : 2006 년 11 월 8 일 ( 수 )
    시간 : 오전 9시 - 오후 5시
    장소 : 코엑스 인터콘티넨탈 하모니 볼룸

The Ultimate Guide to Design Productivity

지난 11월 8일 (수) 코엑스 인터콘티넨탈 하모니 볼룸에서 열렸던 "SOPC World Korea 2006"에서 발표되었던 여러 Presentation 자료들을 다운로드 받으실 수 있습니다...

문의 사항이나 의문점이 있으면 ALTERA Korea나 해당 대리점으로 연락하시기 바랍니다...

Agenda & Technical Sessions

Keynote Speaker: Robert Blake

Robert Blake is the vice president of product planning at Altera Corporation. Mr. Blake is responsible for defining Altera's programmable logic product portfolio, ensuring that Altera's products leverage the most advanced technology and precisely meet customers' cost. He has been developing ASIC and programmable logic for high-speed network applications for over 17 years. Prior to Altera he worked at LSI Logic and Fairchild where he worked developing ASIC technology. He holds a MEng. in Business and Microelectronics and a BSc. in Applied Physics & Electronics from the University of Durham in England.

The Ultimate Guide to Design Productivity  

No matter what business you are in, you need a solution that helps you innovate quickly, differentiate your product, and beat your competition to market. At SOPC World, you will learn how to design faster and smarter, expanding your options while minimizing risk and avoiding wasted effort—ultimately improving your bottom line.

Managing Technology Risk in Volume Applications  

Being productive is just as much about managing technology risk as it is about equipping design engineers with the best tools and devices to meet their schedules. When new semiconductor technologies, such as 65 nm, are released, there is a huge engineering investment to make them stable and reliable for high volumes. There is a delicate balance between realizing the technical advantages of a new process and ensuring that it can be successfully manufactured in production volumes for a broad number of companies. Altera Corporation has the best track record in the programmable logic industry for managing the risk of new technologies while still delivering desired feature and cost improvements. This presentation will share some of Altera's key strategies for managing technology risk.

Embedded Track

This track contains sessions that offer productivity and performance solutions to hardware and software developers.

Implement System-on-a-Programmable Chip (SOPC) in Minutes  

SOPC is the concept of integrating both software and hardware into a single programmable logic device platform to achieve the benefits of software flexibility and the high performance of hardware.

Today's FPGA designs are characterized by higher complexity, performance, and fast time-to-market. New innovative tools are needed to meet FPGA design requirements that are driven by productivity and performance.

This technical session, which includes real examples, will show you how easily Nios^® II embedded processors and SOPC Builder software help you implement FPGA designs.

Using FPGAs to Go Multicore  

FPGAs are an ideal way to leverage the multicore trend using two basic configurations. The first configuration uses the FPGA as a multicore processor offload of an existing CPU or DSP. In this approach, FPGAs can act as hardware accelerators for computation-intensive portions of the host CPU code, improving the system's overall performance, power, and cost. The second configuration uses multiple soft processor cores within an FPGA. This approach offers many advantages, including highly flexible partitioning of the algorithm between CPUs and logic.

This technical session will explain these topics and describe specific commercial successes.

Improving Software Performance Using Hardware Acceleration  

Hardware accelerators are commonly used by system designers to boost system performance. FPGAs are perfectly suited to implement these hardware accelerators.

The Nios II C-to-Hardware Acceleration (C2H) Compiler is a productivity tool that allows Nios II developers to dramatically boost system performance without increasing clock frequency. The Nios II C2H Compiler targets performance-critical ANSI C software functions and automatically converts them into hardware accelerators tightly integrated into the Nios II processor system, providing over 10x performance boosts in many applications with just a few mouse clicks.

This technical session will provide details on how the C2H Compiler helps you dramatically improve productivity and performance.

A Novel Software/Hardware Synchronization Technique for Fast Debugging of SOC Systems - Aldec  

Aldec will present a novel synchronization technique for concurrent debugging of embedded system designs in both the software and hardware domains. Aldec's patented Smart Clock system-bus synchronization tool allows hardware designers to debug HDL code while the most up-to-date version of the processor's software (C/C++/assembler) is also being developed. With this new technique, software developers can simultaneously utilize the latest system bus and peripherals being developed in the hardware domain to do software debugging, including the use of the debugging capabilities offered in Altera's Nios II IDE debugger.

DSP Track

The sessions in this track provide information about using DSP Builder and present solutions that address the latest trends in video and image processing.

Model-Based Design for DSP and FPGA System Implementations - The MathWorks  

The concept of model-based design is quite simple. First, you create a functional implementation model independent of the system. This is an "executable specification," a model that forms the basis of all that is to follow. Once you have verified the model to achieve your system objectives, you can incorporate further detail, such as adding fixed-point effects and RF/ADC non-idealities, and partitioning the design between high-speed fixed-point hardware (an FPGA) and lower speed hardware (a DSP). At every step of the process, you verify that the model achieves the performance goals. The final step is to use the automatic code generation capability to flawlessly implement the model on hardware.

MathWorks engineering will discuss The MathWorks MATLAB and Simulink family of products for Model-Based Design, and how they are used with Altera's DSP Builder for FPGA implementation.

There will also be an edge detection algorithm design and implementation demonstration.

Implementing Video and Image Processing Design Using FPGAs  

The demand for consumer applications such as high-definition televisions (HDTVs) and digital cinema; telecom applications such as voice over IP; and industrial applications such as medical imaging, video surveillance, and photocopiers continues to drive the rapid evolution of video and image processing applications. With major advancements in image capture and display resolutions, advanced compression techniques, and video intelligence, the processing bandwidth required for video applications continues to grow. In addition, rapid changes in standards and higher resolutions are pushing designers away from off-the-shelf technology.

Altera is addressing these trends with modular, programmable video and image processing solutions that offer high performance, flexibility, upgrade ease, low development cost, and a migration path to lower cost when applications mature and volume production ramps.

This technical session will describe key trends in video and image processing, provide insight into video and image processing suites, and explain in detail model-based design for video processing.

Efficient System-Level DSP Design - WiMAX OFDMA Case Study  

DSP system design in FPGAs requires both high-level algorithm and HDL development tools. Altera's DSP Builder integrates these tools by combining the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL synthesis, simulation, and Altera^® development tools. DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. The existing MATLAB functions and Simulink blocks can be combined with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore^® functions to link system-level design and implementation with DSP algorithm development. DSP Builder allows system, algorithm, and hardware designers to share a common development platform.

This technical session, which shows a real-life example of a WiMAX OFDMA design, will describe how Altera's DSP Builder can help you efficiently implement DSP design in FPGAs.

Designing Video Surveillance Equipment Using Altera and TI Technology  

To date, the video surveillance industry has used analog CCTV cameras and interfaces as the basis of surveillance systems. These system components are not easily expandable and have low video resolution with little or no signal processing. However, the next generation of video surveillance systems will replace these components with digital LAN cameras, complex image processing, and video-over-IP routing. They will no longer be simply surveillance camera systems, but scalable, flexible, video communication and cyber-security systems.

This technical session will explain how Altera and TI solutions help you implement video surveillance equipment.

Design Challenges Track

This track contains sessions that offer solutions to some of the challenges faced by system designers.

Seamless, Risk-Free FPGA-to-HardCopy ASIC Migration Flow  

The risk of developing a new product continues to rise as ASIC development costs increase dramatically and the market place continues to change. Changing market requirements, coupled with new competitors, makes ASIC designs a good bet only for a very few designs. Many digital IC companies have recognized the benefits of using FPGAs to demonstrate their intellectual property (IP). Now, by shipping product first with an FPGA and then with a HardCopy ASIC, they are discovering how they can dramatically increase their success.

Altera offers a seamless, risk-free migration from a Stratix^® II FPGA design to a pin-compatible, functionally equivalent HardCopy^® II ASIC. A single, integrated software development platform makes the Quartus^® II software very easy to use, eliminating compatibility problems often found in ASIC design flow due to multiple EDA tools.

This technical session will describe some key attributes of HardCopy II ASICs, the technology of HardCopy II ASICs, and the methodology and process flow of designing HardCopy ASICs using the Quartus II software.

What You Need to Know About High-Speed Design  

High-speed serial links are becoming commonplace across a wide array of applications and are supported by a number of key protocols. High-speed serial links provide many advantages, including support for higher bandwidths, simplified board layout, reduced power requirements, and lower system costs.

However, designing with such high-speed serial links involves challenges in protocol implementation, signal integrity, power management, and PCB layout.

This technical session will provide insights into these challenges and explain how to use FPGAs to overcome these challenges.

Understand and Design for High-Speed Memory Interfaces  

Designing high-speed systems for networking, wireless, computing, storage, test and measurement, and medical imaging applications often requires the use of leading-edge memory devices to maximize your system performance. Newer memory devices such as DDR/DDR2 SDRAM, RLDRAM II, and QDR/QDRII SRAM are being used in such systems.

Integrating these devices into the system creates design challenges such as skew and noise management, signal integrity issues, timing and clock management, and functional verification tasks.

This technical session will explain these design challenges and show you how to resolve them when interfacing FPGAs to advanced memory devices.

Why Does Power Matter?  

Power management is critical in all electronic applications, especially portable battery-powered applications such as cell phones, handhelds, and MP3 Players. Increasingly, with the introduction of wireless standards such as Bluetooth, Wireless Fidelity (WiFi), and 802.11e, many industrial applications are no longer limited by wiring or power infrastructure.

Power is also becoming important in high-end applications such as telecommunications, medical, and industrial automation.

In semiconductor devices, the trend of miniaturization has led towards the 65-nm process technology node, where ineffective power management can lead to system failure and escalating product costs.

Power consumption in semiconductor devices is influenced by factors such as device architecture, process technology, and operating conditions.

This technical session will explain the impact of power on FPGA-based digital systems and identify ways to manage power

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