Stratix Module

Altera's Stratix^™ devices are LUT-based, enhanced memory, DSP-capable devices that use a network of fast routing resources along with efficient logic architecture to achieve optimal performance. The logic, memory, and embedded DSP resources in Stratix devices are ideal for data-path, packet-intensive, DSP, and communications designs. The integrated PLLs combine with an advanced hierarchical clocking network to support clock management and high-speed differential I/O standard requirements.

The Quartus II software provides megafunctions that are optimized to help you take advantage of the I/O, memory, and DSP features of the Stratix device architecture. You can use the MegaWizard^™ Plug-In Manager to create (or modify) design files that contain custom variations of these megafunctions. When you instantiate these megafunctions in a design, the Compiler automatically implements the logic of the megafunctions in appropriate Stratix device resources.

This Stratix tutorial module uses an Altera-provided project and partially completed Block Design File (.bdf) to teach you how to use some of the features of the Stratix architecture. The tutorial guides you through the steps necessary to complete the stratix_filter design by instantiating high-speed LVDS, embedded shift registers, TriMatrix^™ memory, and DSP megafunctions, as shown in the following completed schematic. After you complete the design, you can compile it for a Stratix device.

Section 1: View the stratix_filter Project

The Stratix tutorial module uses the Altera-provided stratix_filter project to demonstrate the implementation of high-speed LVDS, embedded shift registers, TriMatrix^™ memory, and DSP blocks in Stratix devices. The stratix_filter project and design files are installed in the \qdesigns\stratix directory during the installation process.

The top-level stratix_filter Block Design File (.bdf) contains a partially completed, complex finite impulse response (FIR) filter design. The following tutorial section guides you as you open the top-level project and design.

Step 1: Open the stratix_filter Project

To open the stratix_filter project, follow these steps:

1. Choose Open Project (File menu). The Open Project dialog box appears.

2. In the \qdesigns\stratix subdirectory, select the Altera-provided stratix_filter.quartus project file in the Files list.

3. Click Open.

Step 2: Open the stratix_filter Block Design File

To open the stratix_filter BDF, follow these steps:

1. Choose Open (File menu). The Open dialog box appears.

2. In the Files of type list, make sure Device Design Files is selected.

3. In the \qdesigns\stratix subdirectory, select the stratix_filter.bdf file.

4. Click Open. The stratix_filter.bdf appears in the Block Editor.

Section 2: Create & Instantiate a High-Speed LVDS Receiver Megafunction

Stratix devices contain dedicated high-speed PLLs that support differential I/O standards at speeds up to 840 Mbps. You can use these dedicated PLLs to multiply reference clocks and drive high-speed differential SERDES channels. You can instantiate an LVDS receiver megafunction (altlvds_rx) and/or LVDS transmitter megafunction (altlvds_tx) to implement differential I/O standards with a dedicated SERDES.

The following tutorial section teaches you how to use the MegaWizard Plug-In Manager to instantiate an LVDS receiver megafunction in your design.

Step 1: Create an LVDS Receiver Megafunction

You can use the MegaWizard Plug-In Manager (Tools menu) to create a megafunction variation of the altlvds_rx megafunction. To create a two-channel altlvds_rx megafunction with a deserialization factor of eight, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Double-click an empty space in the Block Editor window. The Symbol dialog box appears automatically.

3. In the Symbol dialog box, click MegaWizard Plug-In Manager. The first page of the MegaWizard Plug-In Manager appears.

4. In the first page of the MegaWizard Plug-In Manager, make sure Create a new custom megafunction variation is selected and click Next.

5. Under Which megafunction would you like to customize?, click the + icon to expand the I/O folder, and then select ALTLVDS.

6. Specify the following responses to the remaining prompts on MegaWizard Plug-In Manager page 2a:

Wizard Prompt:	Response:
Which device family will you be using?	Stratix
Which type of output file do you want to create?	AHDL
What name do you want for the output file?	d:\qdesigns\stratix\lvds_in

7. Click Next. MegaWizard Plug-In Manager - ALTLVDS [page 3 of 5] appears.

Step 2: Specify the LVDS Receiver Ports & Parameters

To specify the LVDS receiver ports and parameters, follow these steps:

1. In MegaWizard Plug-In Manager - ALTLVDS [page 3 of 5], select LVDS receiver under This module acts as an.

2. Specify the following responses to the remaining wizard prompts in MegaWizard Plug-In Manager - ALTLVDS page 3:

Wizard Prompt:	Response:
Use which device family?	Make sure Stratix is selected.
What is the number of channels?	Select 2.
What is the deserialization factor?	Select 8.
What is the input data rate?	Type 680.
What is the alignment of data with respect to rx_inclock?	Make sure EDGE_ALIGNED is selected.
Specify the input clock rate by	Make sure clock frequency is selected and type 85 in the box.






3. Click Next. MegaWizard Plug-In Manager - ALTLVDS [page 4 of 5] appears.

Specify the LVDS Receiver Ports & Parameters (cont.)

To continue specifying the ports and parameters for the LVDS receiver megafunction, follow these steps:

1. In MegaWizard Plug-In Manager - ALTLVDS [page 4 of 5], make sure Use the rx_pll_enable input port and Use the "rx_data_align" input port options are turned off under Input Ports.

2. Make sure Register outputs is turned on.

3. Under Output Ports, make sure Use the rx_locked output port is turned off.

4. Turn off Use Common PLLs for Rx and Tx.






5. Make sure AUTO is selected in the rx_outclock resource list.

6. Click Next. The Summary page lists the files that are created for the megafunction.

7. To generate the symbol and return to the Symbol dialog box, click Finish. A preview of the new lvds_in megafunction symbol appears in the Symbol dialog box.

Step 3: Instantiate the LVDS Receiver in the Design

To instantiate the LVDS receiver megafunction in the design, follow these steps:

1. In the Symbol dialog box, click OK. An outline of the lvds_in symbol is attached to the pointer.

2. To place the symbol in the correct location, click the empty space to the right of the data_in[1..0] input pin in the Block Editor window.






3. Choose Save (File menu).

Section 3: Create & Instantiate a FIFO Megafunction

Stratix devices contain TriMatrix memory blocks of three different sizes that you can use to implement various types of memory and FIFO buffers. These memory structures include small M512 memory blocks (32x18 bits), which you can use to implement single-port RAM; and medium M4K memory blocks (128x36 bits) and large MegaRAM^™ memory blocks (4096x144 bits), which you can use to implement single-port, simple dual-port, and true dual-port RAM in the fully synchronous Stratix architecture.

You can use the MegaWizard Plug-In Manager to instantiate a dual-clock FIFO (dcfifo) megafunction. During compilation, the Compiler selects the most appropriate size memory block to implement the FIFO.

Step 1: Create an lpm_fifo+ Megafunction

You can use the MegaWizard Plug-In Manager (Tools menu) to create a variation of the lpm_fifo+ megafunction. To create a 16-bit, dual-clock FIFO with separate read and write clocks, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Double-click an empty space in the Block Editor window. The Symbol dialog box appears automatically.

3. In the Symbol dialog box, click MegaWizard Plug-In Manager. The first page of the MegaWizard Plug-In Manager appears.

4. In the first page of the MegaWizard Plug-In Manager, make sure Create a new custom megafunction variation is selected and click Next.

5. Under Which megafunction would you like to customize?, click the + icon to expand the Storage folder, and then select LPM_FIFO+.

6. Specify the following responses to the remaining wizard prompts:

Wizard Prompt:	Response:
Which device family will you be using?	Stratix
Which type of output file do you want to create?	AHDL
What name do you want for the output file?	d:\qdesigns\stratix\fifo

7. Click Next. MegaWizard Plug-In Manager - FIFO [Page 3 of 8] appears.

Step 2: Specify the lpm_fifo+ Ports & Parameters

To specify the lpm_fifo+ ports and parameters, follow these steps:

1. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - FIFO pages 3 through 7:

Wizard Prompt:	Response:	Page:
Create FIFO for which device family?	Select Stratix.	3
How wide should the FIFO be?	Select 16 bits.	3
How deep should the FIFO be?	Select 256 words.	3
Do you want a common clock for reading and writing the FIFO?	Select No.	3
Which optional output control signals do you want?	Turn off all options except Asynchronous clear.	5
Which type of optimization do you want?	Make sure Use the default optimization setting defined in the logic synthesis style is selected.	7




2. Click Next. The Summary page lists the files that are created for the megafunction.

3. To generate the symbol and return to the Symbol dialog box, click Finish. A preview of the new fifo symbol appears in the Symbol dialog box.

Step 3: Instantiate the lpm_fifo+ Megafunction in the design

To instantiate the lpm_fifo+ megafunction in the design, follow these steps:

1. In the Symbol dialog box, click OK. An outline of the fifo symbol is attached to the pointer.

2. To place the symbol in the correct location, click the empty space to the right of the VCC symbol in the Block Editor window.






3. Choose Save (File menu).

Section 4: Create & Instantiate a Tapped Shift Register Megafunction

The new altshift_taps megafunction instantiates a RAM-based shift register with taps that is specifically optimized for implementation in Stratix devices. Previous implementation of tapped shift registers required multiple instances of shift register symbols.

The following tutorial section teaches you how to use the MegaWizard Plug-In Manager to create and instantiate a 16-bit wide, 16-bit deep shift register with taps.

Step 1: Create an altshift_taps Megafunction

You can use the MegaWizard Plug-In Manager (Tools menu) to create a variation of the altshift_taps megafunction. To create a 16-bit wide, 16-bit deep shift register with taps, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Double-click an empty space in the Block Editor window. The Symbol dialog box appears automatically.

3. In the Symbol dialog box, click MegaWizard Plug-In Manager. The first page of the MegaWizard Plug-In Manager appears.

4. In the first page of the MegaWizard Plug-In Manager, make sure Create a new custom megafunction variation is selected and click Next.

5. Under Which megafunction would you like to customize?, click the + icon to expand the Storage folder, and then select ALTSHIFT_TAPS.

6. Specify the following responses to the remaining wizard prompts:

Wizard Prompt:	Response:
Which device family will you be using?	Stratix
Which type of output file do you want to create?	AHDL
What name do you want for the output file?	d:\qdesigns\stratix\tap

7. Click Next. MegaWizard Plug-In Manager - altshift_taps [Page 3 of 4] appears.

Step 2: Specify altshift_taps Ports & Parameters

To specify the altshift_taps ports and parameters, follow these steps:

1. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - altshift_taps page 3:

Wizard Prompt:	Response:
How wide should the 'shift_in' input and the 'shift_out' output buses be?	Select 16 bits.
How many taps would you like?	Select 4.
How wide should the distance between taps be?	Select 16.
Create a clock enable port	Make sure this option is turned off.









2. Click Next. The Summary page lists the files that are created for the megafunction.

3. To generate the symbol and return to the Symbol dialog box, click Finish. A preview of the new tap symbol appears in the Symbol dialog box.

Step 3: Instantiate the altshift_taps Megafunction in the Design

To instantiate the altshift_taps megafunction in the design, follow these steps:

1. In the Symbol dialog box, click OK. An outline of the tap symbol is attached to the pointer.

2. To place the symbol in the correct location, click the empty space to the right of the fifo symbol in the Block Editor window.






3. Choose Save (File menu).

Section 5: Create & Instantiate a ROM Megafunction

In addition to true dual-port memory, the TriMatrix memory in Stratix devices also supports various simple dual-port and single-port RAM and ROM memory configurations. When you configure a memory block as RAM or ROM, you can use a Memory Initialization File (.mif) to pre-load the initial contents of the memory.

This tutorial section shows you how to use the MegaWizard Plug-In Manager to create one of the four single-port ROM (altsyncram) megafunctions in the design. Each of the ROM megafunctions uses a separate Altera-provided MIF to pre-load the initial contents of the memory. These ROM megafunctions in the design feed the data to the Multiply-Add megafunction created later in this tutorial.

Step 1: Create an altsyncram Megafunction

To create one of the 16-bit wide, 16-bit deep altsyncram megafunctions used in the design, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Double-click an empty space in the Block Editor window. The Symbol dialog box appears automatically.

3. In the Symbol dialog box, click MegaWizard Plug-In Manager. The first page of the MegaWizard Plug-In Manager appears.

4. In the first page of the MegaWizard Plug-In Manager, make sure Create a new custom megafunction variation is selected and click Next.

5. Under Which megafunction would you like to customize?, click the + icon to expand the Storage folder, and then select ALTSYNCRAM.

6. Specify the following responses to the remaining wizard prompts:

Wizard Prompt:	Response:
Which device family will you be using?	Stratix
Which type of output file do you want to create?	AHDL
What name do you want for the output file?	d:\qdesigns\stratix\ram_0c

7. Click Next. MegaWizard Plug-In Manager - ALTSYNCRAM [Page 3 of 10] appears.

Step 2: Specify altsyncram Ports & Parameters

To specify the altsyncram ports and parameters, follow these steps:

1. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - ALTSYNCRAM pages 3 through 5:

Wizard Prompt:	Response:	Page:
How will you be using the altsyncram?	Select With one read port.	3
How do you want to specify the memory size?	Make sure As a number of bits is selected.	3
How many bits of memory?	Make sure 256 is selected.	4
How wide should the 'q_a' output bus be?	Select 16.	4
Which clocking method do you want to use?	Make sure Single clock is selected.	5




2. Click Next. MegaWizard Plug-In Manager - ALTSYNCRAM [Page 7 of 10] appears.

Specify altsyncram Ports & Parameters (cont.)

To continue specifying the altsyncram ports and parameters, follow these steps:

1. Specify the following responses to the remaining wizard prompts in MegaWizard Plug-In Manager - ALTSYNCRAM pages 7 through 9:

Wizard Prompt:	Response:	Page:
Which ports should be registered?	Turn on Read output port(s) 'q'.	7
What should the RAM block type be?	Make sure Auto is selected.	9
Do you want to specify the initial contents of the memory?	Select Yes and specify the Altera-provided D:\qdesigns\stratix\ram_0c.mif file in the File name box.	9






2. Click Next. The Summary page lists the files that are created for the megafunction.

3. To generate the symbol and return to the Symbol dialog box, click Finish. A preview of the new ram_0c symbol appears in the Symbol dialog box.

Step 3: Instantiate the altsyncram Megafunction in the Design

To instantiate the altsyncram megafunction in the design, follow these steps:

1. In the Symbol dialog box, click OK. An outline of the ram_0c symbol is attached to the pointer.

2. To place the symbol in the correct location, click the empty space to the right of the q[3..0] output node line of the memory_address symbol in the Block Editor window.






3. Choose Save (File menu).

Section 6: Create & Instantiate a Multiply-Add Megafunction

Each Stratix device contains high-speed DSP blocks that allow you to efficiently implement DSP multiply functions in dedicated hardware without using other logic elements (LEs). You can use the DSP blocks to implement arithmetic functions such as multiply and multiply-accumulate with or without using add, subtract, or accumulate functions.

Each DSP block contains several multipliers that you can configure to implement multipliers with widths up to 9 bits (eight multipliers per block), 18 bits (four multipliers per block), or 36 bits (one multiplier per block). These multipliers can optionally feed an adder or accumulator within the block. You can use these dedicated DSP blocks to simplify routing and increase performance by ensuring that all related connections are located within the DSP block.

You can use the MegaWizard Plug-In Manager to create and instantiate DSP functions, such as a multiply-add (altmult_add) megafunction. When you compile a design that contains DSP functions, the Compiler automatically implements the logic of these functions in DSP blocks. The following tutorial module teaches you how to use the MegaWizard Plug-In Manager to create and instantiate a multiply-add megafunction that is implemented in a DSP block.

Step 1: Create an altmult_add Megafunction

To create an altmult_add megafunction that implements four pipelined 16-bit multipliers feeding a single 34-bit adder, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Double-click an empty space in the Block Editor window. The Symbol dialog box appears automatically.

3. In the Symbol dialog box, click MegaWizard Plug-In Manager. The first page of the MegaWizard Plug-In Manager appears.

4. In the first page of the MegaWizard Plug-In Manager, make sure Create a new custom megafunction variation is selected and click Next.

5. Under Which megafunction would you like to customize?, click the + icon to expand the arithmetic folder, and then select ALTMULT_ADD.

6. Specify the following responses to the remaining wizard prompts:

Wizard Prompt:	Response:
Which device family will you be using?	Stratix
Which type of output file do you want to create?	AHDL
What name do you want for the output file?	d:\qdesigns\stratix\mac

7. Click Next. MegaWizard Plug-In Manager - ALTMULT_ADD [Page 1 of 4] appears.

Step 2: Specify altmult_add Ports & Parameters

To specify the altmult_add ports and parameters, follow these steps:

1. Specify the following responses to the wizard prompts in MegaWizard Plug-In Manager - ALTMULT_ADD page 1:

Wizard Prompt:	Response:
What is the number of multipliers?	Select 4 and make sure All multipliers have similar configurations is turned on.
How wide should the A input buses be?	Make sure 16 bits is selected.
How wide should the B input buses be?	Make sure 16 bits is selected.
How wide should the 'result' output bus be?	Make sure 34 bits is selected.






2. To accept the defaults for the remaining questions and generate the symbol, click Finish. A preview of the new symbol appears in the Symbol dialog box.

Step 3: Instantiate the altmult_add Megafunction in the Design

To instantiate the altmult_add megafunction in the design, follow these steps:

1. In the Symbol dialog box, click OK. An outline of the mac symbol is attached to the pointer.

2. To place the symbol in the correct location, click the empty space to the right of the tap_bus[63..48] output node line in the Block Editor window.






3. Choose Save (File menu).

Section 7: Connect the Symbols

You can complete the schematic by connecting the symbols with the appropriate node and bus lines. The following tutorial section shows you how to complete the stratix_filter.bdf file by connecting the symbols, as shown in the following completed schematic:

Step 1: Make Bus Connections

To make bus connections between symbols, follow these steps:

1. With the Selection and Smart Drawing Tool, click the pinstub of the data_in[1..0] input pin to define the start of the bus, and then drag the pointer to draw a line that connects to the rx_in[1..0] input port of the lvds_in symbol.

Aligning the symbols with node and bus lines as described in the preceding topics and illustrations creates many of the necessary node and bus connections automatically.






2. Repeat step 1 to make the additional bus connections between the symbols shown in the following table:

Make Bus Connection From:	To:
rx_out[15..0] output port of lvds_in symbol	data[15..0] input port of fifo symbol.
q[15..0] output port of fifo symbol	shiftin[15..0] input port of tap symbol
taps[63..0] output port of tap symbol	tap_bus[63..0] bus line
q[3..0] output port of memory_address symbol	address[3..0] input port of ram_0c symbol
q[15..0] output port of ram_0c symbol	dataa_0[15..0] input port of mac symbol.
result[33..0] output port of mac symbol	OUTPUT pin out[33..0]

3. Choose Save (File menu).

Step 2: Make Node Connections

To make node connections, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Click the pinstub of the lvds_clock input pin to define the start of the node, and then drag the pointer to draw a line that connects to the rx_inclock input port of the lvds_in symbol.

3. Repeat step 2 to make the additional node connections between the symbols shown in the following table:

Make Node Connection From:	To:
rx_outclock output port of lvds_in symbol	wrclk input clock port of fifo symbol
Input pinstub of VCC symbol	wrreq input port of fifo symbol
Input pinstub of VCC symbol	rdreq input port of fifo symbol






4. Choose Save (File menu).

Step 3: Make Connections by Name

To create nodes that can be connected by name, follow these steps:

1. Click the Selection and Smart Drawing Tool button on the toolbar.

2. Draw a node line from the fifo symbol's rdclock input into an empty space.

3. With the Selection and Smart Drawing Tool, select the node line that is connected to the rdclock clock input port of the fifo symbol.

4. Choose Properties (right button pop-up menu). The General tab of the Node Properties dialog box appears automatically.

5. In the Name box, type clk as the name of the node.

6. Click OK. The signal clk is added to the node, and the name appears above the node line.

7. Repeat steps 1 through 6 to draw and name the nodes shown in the following table:

Draw Node From:	To:	Name Node:
aclr input port of fifo symbol	Empty space	clr
clock input port of tap symbol	Empty space	clk
clk0 input port of of mac symbol	Empty space	clk






8. Choose Save (File menu). The stratix_filter design is complete.

Section 8: Compile the Design

Once you have completed the stratix_filter design, you can run the Compiler to check the design for errors, synthesize the logic, fit the design into a Stratix device, and generate output files for simulation, timing analysis, and device programming.

The following tutorial section teaches you how to specify a Stratix device as the target for compilation and run the Compiler.

Step 1: Specify the Target Device

To specify a Stratix device as the target device for compilation, follow these steps:

1. Choose Settings (Assignments menu).

2. In the Category list, select Device under Compiler Settings.

3. In the Family list, select Stratix.

4. If necessary, click Yes if you are asked whether you want to allow the Quartus II software to select a device and remove any pin assignments.

5. Under Target device, select Specific device selected in "Available devices" list.

6. Under Show in "Available devices" list, select the following options:

1. In the Package list, select FBGA.

2. In the Pin count list, select 780.

3. In the Speed grade list, select 6.

7. In the Available devices list, select EP1S25F780C6.






8. Click OK.

Step 2: Run the Compiler

During compilation, the current Compiler settings control design processing. The Compiler automatically locates and uses all design and project files, including the MIFs containing the initial content of the memories in the design.

To compile the stratix_filter design for a Stratix device, follow these steps:

1. Choose Start Compilation (Processing menu).

2. When you receive a message indicating that compilation was successful, click OK to close the message box. The stratix_filter design is compiled for a Stratix device.

If the Compiler displays any error messages in the Messages window, select the message and choose Locate (right button pop-up menu) to find its source(s), and/or choose Help (right button pop-up menu) to display Help on the message.

If you want to start another tutorial module, return to Start the Tutorial.