Avoiding Timing Issues with Clock Skew

In large projects that consist of more than one clock signal, it will be necessary to place generated clock lines onto low-skew clock buses in order to avoid timing problems. The Altera Flex device has two low-skew clock buses available. During the compile, MaxPlus will automatically assign a signal to one of the buses. In our project, we were using both the Flex board's clock as well as a generated clock.  The compiler automatically put the 25MHz input signal from the Flex board onto the bus, but it failed to identify our main clock (called Clock) as a global signal. This caused many timing problems between the modules and inevitably caused our project not to work.

In order to identify a signal as a global signal, you will need to add the following component to your code in the module where you are generating your clock signal.  You will also need to use MaxPlusII 8.1 or higher. 

component Global
port (a_in : in std_logic;
       a_out : out std_logic);
end component;

NOTE: Don’t worry about that fact that there is not a file in your working directory called "global.vhd". It compiles just fine without one.

In the architectural section of the VHD file, you will need to pass in your generated clock signal into this component and capture its returned value. This example shows a signal called "dblclock" using the global component.  The output signal "clock" can then be passed into lower modules.

GCLK : GLOBAL
port map(a_in => dblclock,
              a_out => clock);

If you are not sure whether your clock is on a low-skew bus or not, you can consult the RPT file generated during the compile. It will have the word "GLOBAL" followed by the signal in parenthesis if it is on one of the low-skew clock buses. Here is an example of how this should appear :

-- Node name is ':284' = 'col_address0'
-- Equation name is 'col_address0', location is LC2_B4, type is buried.
col_address0 = DFFE( _EQ001, GLOBAL( BrdClock), VCC, VCC, VCC);
_EQ001 = !col_address0 & !_LC1_B52 & _LC2_D49
# col_address0 & _LC1_B52 & _LC2_D49
# col_address0 & !_LC6_B21;

In this case, the node it is referring to is col_address0, which is part of the video module. This module uses BrdClock as its clock, so this should be on a low-skew clock line.

To verify that the flip-flops are using the global clock, look at the report file at the node in question. It should have the phrase "GLOBAL( )" to identify the clock.

-- Node name is '|top_spim:TOP|Idecode:ID|:79' = '|top_spim:TOP|Idecode:ID.Addresult_D0'
-- Equation name is '_LC7_E11', type is buried
_LC7_E11 = DFFE( _EQ427, GLOBAL( dblclock), VCC, VCC, VCC);
_EQ427 = _LC4_E4 & !_LC5_I27;

In this case the node Addresult_D0 uses the calculated global signal. If you do not see the GLOBAL(signal), then the signal you are using is not on a global line.