MAX 7000, 7000A, 7000E, 7000S

GND - If the dedicated input pins are left floating, then they no longer remain in the saturation or cutoff region of the IV graph. Potentially the device could start drawing an excessive amount of current causing possible damage to the pin and the device.

Can be used as IOs

N/A

MUST be connected to GND. The state of the unused IOs is unknown during user mode. Therefore, the pins could be switching, be low or high. Please see Atlas solution: Why does the MAX+PLUS^® II software allow me to connect all my unused I/O pins to ground for a MAX^® 7000AE device, but for other MAX 7000 devices it says I must leave them unconnected?

MAX 7000AE, 7000B

GND - If the dedicated input pins are left floating, then they no longer remain in the saturation or cutoff region of the IV graph. Potentially the device could start drawing an excessive amount of current causing possible damage to the pin and the device.

Can be used as IOs

N/A

Can be connected to GND or left unconnected. Please see Atlas solution: Why does the MAX+PLUS^® II software allow me to connect all my unused I/O pins to ground for a MAX^® 7000AE device, but for other MAX 7000 devices it says I must leave them unconnected?

ACEX & FLEX

GND - If the dedicated input pins are left floating, then they no longer remain in the saturation or cutoff region of the IV graph. Potentially the device could start drawing an excessive amount of current causing possible damage to the pin and the device.

AN 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices)

VCC_CLKLK and GND_CLKLK are the power and ground for the ClockLock and ClockBoost circuitry. If the ClockLock or ClockBoost circuitry is not used, the VCC_CLKLK and GND_CLKLK pin should be connected to VCCINT or GNDINT, respectively.

MUST be connected to GND. The state of the unused IOs is unknown during user mode.

APEX

GND - If the dedicated input pins are left floating, then they no longer remain in the saturation or cutoff region of the IV graph. Potentially the device could start drawing an excessive amount of current causing possible damage to the pin and the device.

AN 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices)

CLKLK_FB1p and CLKLK_FB2p should be connected to GND. CLKLK_OUT1p and CLKLK_OUT2p are floating, therefore, they should be pulled down or connected to ground. CLKLK_ENA is recommended to be connected to VCCINT. However, either VCCINT or GND are acceptable since CLKLK_ENA is a floating input. VCC_CLKLK and GND_CLKLK are the power and ground for the ClockLock and ClockBoost circuitry. If the ClockLock or ClockBoost circuitry is not used, the VCC_CLKLK and GND_CLKLK pin should be connected to VCCINT or GNDINT, respectively.

VCC_CLKOUT and GND_CLKOUT are the power or ground for the external output of a PLL. If the PLL or external output is not used, VCC_CLKOUT and GND_CLKOUT should be connected to VCCIO or GNDIO, respectively.

Dependent on the user. Please see Atlas solution: How should I connect my unused APEX^TM 20K or APEX 20KE I/O pins?

Mercury

GND - If the dedicated input pins are left floating, then they no longer remain in the saturation or cutoff region of the IV graph. Potentially the device could start drawing an excessive amount of current causing possible damage to the pin and the device.

AN 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices)

CLKLK_FB1p and CLKLK_FB2p should be connected to GND. CLKLK_OUT1p and CLKLK_OUT2p are floating, therefore, they should be pulled down or connected to ground. CLKLK_ENA is recommended to be connected to VCCINT. However, either VCCINT or GND are acceptable since CLKLK_ENA is a floating input.

Dependent on the user. Please see Atlas solution: How should I connect my unused APEX^TM 20K or APEX 20KE I/O pins?