Quartus® II support for User Defined Primitives (UDPs) is described below. Section numbers match those in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.
| Section | Verilog HDL Construct | Quartus II Support Note (1) |
|---|---|---|
| 8.2 | Combinational UDPs | Supported. |
| 8.3 | Level-Sensitive Sequential UDPs | Supported. |
| 8.4 | Edge-Sensitive Sequential UDPs | Supported. |
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