Verilog HDL

Data Types

Quartus® II support for data types is described below. Section numbers match those in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

Section Verilog HDL Construct Quartus II Support     Note (1)
3.2.2 Registers Supported except for Real and Realtime Registers. See Section 3.9, below.
3.3 Vectors Supported.
3.4 Strengths Not supported.
3.4.1 Charge Strength Not supported.
3.4.2 Drive Strength Not supported.
3.5 Implicit Declarations Supported.
3.6 Net Initialization Not supported. Undriven nets are connected to GND.
3.7 Nets Supported as defined in subsections 3.7.1 through 3.7.5.
3.7.1 wire and tri Nets Supported.
3.7.2 Wired Nets (wor, wand,trior, and triand Nets) Not supported.
3.7.3 trireg Nets Not supported.
3.7.4 tri0 and tri1 Nets Not supported.
3.7.5 supply0 and supply1 Nets Not supported.
3.8 Memories Supported.
3.9 Integers, Reals, Times, and Realtimes Integers and Times are supported. Reals and Realtimes are not supported.
3.10 Parameters Supported.


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