See Also

Continuous Assignments assign values to nets, directing the Compiler to create simple gates and logical connections. Continuous Assignments are reevaluated whenever any input on the right of the assignment changes value.

The Continuous Assignments shown in the following example create an AND gate and connect two nodes, respectively. These statements are executed concurrently.

module simpsig (a, b, e, c, d);

input  a, b, e;
output c, d;

    assign c = a & b;
    assign d = e;

endmodule

In this example, the signal c receives the value of a & b, and the signal d receives the value of e.

For more information, see the following sections of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual:

• Section 4.1: Operators
• Section 6.1: Continuous Assignments

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