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Displays information regarding SERDES receiver with Dynamic Phase Alignment (DPA) usage, which is implemented using the altpll megafunction in Stratix™ GX devices, including parameter values you specified when instantiating the PLL. This section is omitted if the design does not include SERDES receivers.
Information is provided as follows:
| Heading | Description | Value |
|---|---|---|
| Name | Shows the instance name of the SERDES receiver. | <SERDES receiver instance> |
| Clock0 | Shows the signal source for the clock0 input of the SERDES receiver. |
<signal source name> |
| Core Clock | Shows the signal source for the coreclk input of the SERDES receiver. |
<signal source name> |
| Data Realigner | Shows the signal source for the bitslip input of the SERDES receiver. |
<signal source name> |
| Reset | Shows the signal source for the dpareset input of the SERDES receiver. |
<signal source name> |
| DPLL Reset | Shows the signal source for the dpllreset input of the SERDES receiver. |
<signal source name> |
| Data Width | Shows the data width of the output for the SERDES receiver. | <data width> |
| FIFO | Shows whether FIFO is enabled for the SERDES receiver. | Enabled | Disabled |
The following example shows a portion of the Differential I/O Receiver with Dynamic Phase Alignment section generated for a sample design:
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