Very High Speed Integrated Circuit (VHSIC) Hardware Description Language.

You can create a VHDL Design File (.vhd) with the Quartus^® II Text Editor or any standard text editor and compile it directly with the Quartus II software. You can also generate an EDIF 2 0 0 or 3 0 0 netlist file from a VHDL design that has been processed with a VHDL synthesis tool, then import the file into the Quartus II software as an EDIF Input File (.edf).

The Quartus II Compiler can also generate a VHDL Output File (.vho) that contains functional and timing information for simulation with a standard VHDL simulator.

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