A Quartus^® II simulation mode that uses the Compiler database to simulate the logical and timing performance of a design. Timing simulation uses a fully compiled netlist that includes estimated or actual timing information. You can use Tcl commands, a Vector Waveform File (.vwf), or a text-based Vector File (.vec) to provide vector stimuli. This type of simulation also allows you to check setup and hold times, detect glitches, and check simulation coverage (the ratio of nodes simulated to the total number of nodes in the design).

Because simulation is performed using a database generated after logic synthesis, partitioning, and fitting are performed, timing simulation allows you to simulate only the nodes in a project that have not been removed by logic optimization.