Specifies the maximum acceptable clock hold (tH) time for the input (data) pin. The following table prioritizes each legal assignment type, and shows which paths are affected when assigned. Priority 1 assignments take precedence over priority 2 assignments, and so on. Within a priority level, the most stringent requirement takes precedence. Specifying a point-to-point th Requirement assignment may increase the time necessary for timing-driven compilation.
| Priority Level | Assignment Type/Location | Affected Path(s) |
|---|---|---|
| 1 |
Point-to-point assignment from input or bidirectional pin to a register. |
Affects the specified pin to register paths controlled by any clock(s). |
| 2 |
Point-to-point assignment from clock to register. |
Affects any pin to register paths controlled by the clock. |
| 2 | Point-to-point assignment from clock to input or bidirectional pin. | Affects the specified pin to any register path controlled by the clock. |
| 3 | Single point assignment to a register. | Affects the register and any pin(s) or clock(s) feeding the register. |
| 3 | Single point assignment to an input or bidirectional pin. |
Affects the pin and any register(s) fed by the pin and any clock(s) feeding the register. |
| 4 | Single point assignment to a clock. | Affects any registers fed by the clock. |
| 5 | Global | All remaining paths. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |