Specifies the maximum acceptable clock-to-output delay to the output pin. The clock-to-output delay is the time required to obtain a valid output at an output pin that is fed by a register after a clock signal transition on an input pin that clocks the register. This time always represents an external pin-to-pin delay. The following table prioritizes each legal assignment type, and shows which paths are affected when assigned. Priority 1 assignments take precedence over priority 2 assignments, and so on. Within a priority level, the most stringent requirement takes precedence. Specifying a point-to-point tco Requirement assignment may increase the time necessary for timing-driven compilation.
| Priority Level | Assignment Type/Location | Affected Path(s) |
|---|---|---|
| 1 |
Point-to-point assignment from register to output or bidirectional pin. |
All paths from the register to pin. |
| 2 |
Point-to-point assignment from clock to register. Point-to-point assignment from clock to output or bidirectional pin. |
All paths from the clock to the register or pin. |
| 3 |
Single point assignment to register. Single point assignment to output or bidirectional pin. |
All paths that feed the register or pin. |
| 4 | Single point assignment to a clock. | All paths from the clock. |
| 5 | Global | All remaining paths. |
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