A design entity, such as an Altera-provided megafunction or user-created megafunction or macrofunction, that is below another design entity in a project hierarchy. The top-level design entity that contains the subdesign is the "parent entity" for that subdesign.

You can set a subdesign as the compilation focus; however, when you do so, the Compiler uses the parameters and assignments from the top-level, parent entity of that subdesign during compilation.

When you try to set a subdesign as the simulation focus, the Quartus^® II software automatically creates a top-level design entity for that subdesign, and sets the new top-level design entity as the simulation focus.

Altera^® provides libraries of megafunctions and the corresponding AHDL Include Files (.inc) in the \quartus\libraries\megafunctions and \quartus\libraries\others\maxplus2 directories. Component Declarations for functions supported by VHDL are provided in the maxplus2 and megacore packages in the \quartus\libraries\vhdlnn\altera\ directory, (where nn is "87" or "93"), and in the lpm_components package in the \quartus\libraries\vhdlnn\lpm\ directory.