A state is implemented in a device as a pattern of 1s and 0s (bits) that are the outputs of multiple flipflops (collectively called a state machine state register). States can be defined in an AHDL Text Design File (.tdf), a Vector File (.vec), a Vector Waveform File (.vwf), a VHDL Design File (.vhd), or a Verilog Design File (.v), and are reported in the State Machines section of the Compilation Report.