A conditional assignment of a state to the state machine name. State transitions are created by conditionally assigning the states with a single behavioral construct.

In AHDL, state transitions are created with Case or Truth Table Statements. State transitions occur on the rising edge of the clock.

In VHDL and Verilog HDL, state transitions are created with Case Statements. You must also provide a Wait Statement in VHDL to cause each state transition to occur on a clock edge. In Verilog HDL, the Always Construct that contains the Case Statement must also contain an Event Control that causes each state transition to occur on a clock edge.

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