A configuration scheme in which an external controller passes configuration data to one or more Altera^® devices supported by the Quartus^® II software, except MAX^® 3000 and MAX 7000 devices, via a serial data stream.

The device is treated as a slave device with a 5-wire interface to the external controller. The external controller can be an intelligent host such as a microcontroller or CPU, or the Quartus II Programmer. For Altera devices, the external controller can also be a serial configuration device, such as the EPC2 or EPC16 configuration device.

The Quartus II Compiler automatically generates SRAM Object Files (.sof) that contain the data for configuring Altera devices in a PS configuration scheme.

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