A logic option that prevents a register from minimizing away during synthesis and prevents sequential netlist optimizations. Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers.

This option is useful for preserving a register so you can observe it during Simulation. It is also useful for creating a preliminary version of the design in which secondary signals are not specified.

This option is ignored if it is applied to anything other than a register. This option is available for all Altera^® devices supported by the Quartus^® II software.